var_div.tdf

来自「ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提」· TDF 代码 · 共 52 行

TITLE "var_div Frequency Divider Module"; 
-- Version 2.0, January 29, 1998
-- Copyright Rune Baeverrud
-- You may use or distribute this function freely,
-- provided you do not remove this copyright notice.
-- If you have questions or comments, feel free to
-- contact me by email at [e-mail] 
-- World Wide WEB: http://www.acte.no/freecore

PARAMETERS
(
  WIDTH = 4
);

INCLUDE "lpm_counter";
INCLUDE "lpm_compare";

SUBDESIGN var_div
(
  SysClk           : INPUT;
  cnt_en           : INPUT = VCC;
  sclr             : INPUT = GND;
  d[WIDTH-1..0]    : INPUT;

  Every_N          : OUTPUT;
  q[WIDTH-1..0]    : OUTPUT;
)

VARIABLE
  counter          : LPM_COUNTER WITH (LPM_WIDTH = WIDTH);
  max_cnt          : NODE;
  Deglitch         : DFF;

BEGIN
  max_cnt = LPM_COMPARE(d[], counter.q[],,)
            WITH (LPM_WIDTH = WIDTH)
            RETURNS (.aeb);
 
  counter.clock  = SysClk;
  counter.cnt_en = cnt_en;
  counter.sclr   = (max_cnt AND cnt_en) OR sclr;

  Deglitch     = max_cnt AND cnt_en;
  Deglitch.clk = SysClk;
  Every_n      = Deglitch;

  q[] = counter.q[];
END;