📄 sdr_sdram_tb.v
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/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller test bench
* MODULE NAME: sdr_sdram_tb()
* COMPANY: Northwest Logic, Inc.
* www.nwlogic.com
*
* REVISION HISTORY:
*
* Revision 1.0 05/12/2000 Initial Release.
*
* 1.1 07/12/2000 Modified to support burst terminate and precharge
* during full page accesses.
*
* FUNCTIONAL DESCRIPTION:
*
* This module is the test bench for the SDR SDRAM controller.
*
* Trade Secret of Northwest Logic, Inc. Do not disclose.
* Copyright Northwest Logic, Inc., 2000. All rights reserved.
*
* Copying or other reproduction of this code except
* for archival purposes is prohibited without the prior written
* consent of Northwest Logic.
*
* RESTRICTED RIGHTS LEGEND
*
* Use, duplication, or disclosure by the Government is subject to
* restrictions as set forth in paragraph (b) (3) (B) of the Rights
* in Technical Data and Computer Software clause in DAR 7-104.9(a).
*
******************************************************************************/
`timescale 1ps / 1ps
module sdr_sdram_tb();
// defines for the testbench
`define BL 8 // burst length
`define CL 3 // cas latency
`define RCD 2 // RCD
`define LOOP_LENGTH 1024 // memory test loop length
`include "params.v"
reg clk; // Generated System Clock
reg clk2; // staggered system clock for sdram models
reg reset_n; // Reset
reg [2:0] cmd;
reg [`ASIZE-1:0] addr;
reg ref_ack;
reg [`DSIZE-1:0] datain;
reg [`DSIZE/8-1:0] dm;
wire cmdack;
wire [`DSIZE-1:0] dataout;
wire [11:0] sa;
wire [1:0] ba;
wire [1:0] cs_n;
wire cke;
wire ras_n;
wire cas_n;
wire we_n;
wire [`DSIZE-1:0] dq;
wire [`DSIZE/8-1:0] dqm;
reg [`ASIZE-1:0] test_data;
reg [`DSIZE-1:0] test_addr;
reg [11:0] mode_reg;
integer j;
integer x,y,z;
integer bl;
// SDR SDRAM controller
sdr_sdram sdr_sdram1 (
.CLK(clk),
.RESET_N(reset_n),
.ADDR(addr),
.CMD(cmd),
.CMDACK(cmdack),
.DATAIN(datain),
.DATAOUT(dataout),
.DM(dm),
.SA(sa),
.BA(ba),
.CS_N(cs_n),
.CKE(cke),
.RAS_N(ras_n),
.CAS_N(cas_n),
.WE_N(we_n),
.DQ(dq),
.DQM(dqm)
);
// micron memory models
mt48lc8m16a2 mem00 (.Dq(dq[15:0]),
.Addr(sa[11:0]),
.Ba(ba),
.Clk(clk2),
.Cke(cke),
.Cs_n(cs_n[0]),
.Cas_n(cas_n),
.Ras_n(ras_n),
.We_n(we_n),
.Dqm(dqm[1:0]));
mt48lc8m16a2 mem01 (.Dq(dq[31:16]),
.Addr(sa[11:0]),
.Ba(ba),
.Clk(clk2),
.Cke(cke),
.Cs_n(cs_n[0]),
.Cas_n(cas_n),
.Ras_n(ras_n),
.We_n(we_n),
.Dqm(dqm[3:2]));
mt48lc8m16a2 mem10 (.Dq(dq[15:0]),
.Addr(sa[11:0]),
.Ba(ba),
.Clk(clk2),
.Cke(cke),
.Cs_n(cs_n[1]),
.Cas_n(cas_n),
.Ras_n(ras_n),
.We_n(we_n),
.Dqm(dqm[1:0]));
mt48lc8m16a2 mem11 (.Dq(dq[31:16]),
.Addr(sa[11:0]),
.Ba(ba),
.Clk(clk2),
.Cke(cke),
.Cs_n(cs_n[1]),
.Cas_n(cas_n),
.Ras_n(ras_n),
.We_n(we_n),
.Dqm(dqm[3:2]));
initial begin
clk = 1;
clk2 = 1;
reset_n = 0; // reset the system
#100000 reset_n = 1;
end
// system clocks
//133mhz clock always block
always begin
#2750 clk2 = ~clk2;
#1000 clk = ~clk;
end
//100mhz clock always block
//always begin
// #3 clk2 = ~clk2;
// #2 clk = ~clk;
//end
// write_burst(address, start_value, data_mask, RCD, BL)
//
// This task performs a write access of size BL
// at SDRAM address to the SDRAM controller
//
// address : Address in SDRAM to start the burst access
// start_value : Starting value for the burst write sequence. The write burst task
// simply increments the data values from the start_value.
// data_mask : Byte data mask for all cycles in the burst.
// RCD : RCD value that was set during configuration
// BL : BL is the burst length the devices have been configured for.
task burst_write;
input [`ASIZE-1 : 0] address;
input [`DSIZE-1 : 0] start_value;
input [`DSIZE/8-1 : 0] data_mask;
input [1 : 0] RCD;
input [3 : 0] BL;
integer i;
begin
addr <= address;
cmd <= 3'b010; // Issue a WRITEA command
datain <= start_value; // Assert the first data value
dm <= data_mask;
@(cmdack==1); // wait for the ack from the controller
@(posedge clk);
cmd <= 3'b000;
for (i=1 ; i<=(RCD-2); i=i+1) // wait for RAS to CAS to expire
@(posedge clk);
for(i = 1; i <= BL; i = i + 1) // loop from 1 to BL
begin
#1000;
datain <= start_value + i; // clock the data into the controller
@(posedge clk);
end
dm <= 0;
end
endtask
// burst_read(address, start_value, CL, RCD, BL)
//
// This task performs a read access of size BL
// at SDRAM address to the SDRAM controller
//
// address : Address in SDRAM to start the burst access
// start_value : Starting value for the burst read sequence. The read burst task
// simply increments and compares the data values from the start_value.
// CL : CAS latency the sdram devices have been configured for.
// RCD : RCD value the controller has been configured for.
// BL : BL is the burst length the sdram devices have been configured for
task burst_read;
input [`ASIZE-1 : 0] address;
input [`DSIZE-1 : 0] start_value;
input [1 : 0] CL;
input [1 : 0] RCD;
input [3 : 0] BL;
integer i;
reg [`DSIZE-1 : 0] read_data;
begin
addr <= address;
cmd <= 3'b001; // Issue the READA command
@(cmdack == 1); // wait for an ack from the controller
@(posedge clk);
#1000;
cmd <= 3'b000; // Issue a NOP
for (i=1 ; i<=(CL+RCD+1); i=i+1) // wait for RAS to CAS to expire
@(posedge clk);
for(i = 1; i <= BL; i = i + 1) // loop from 1 to burst length(BL), collecting and comparing the data
begin
@(posedge clk);
read_data <= dataout;
#2000;
if (read_data !== start_value + i - 1)
begin
$display("Read error at %h read %h expected %h", (addr+i-1), read_data, (start_value + i -1));
$stop;
end
end
#1000000;
cmd <= 3'b100; // issue a precharge command to close the page
@(posedge clk);
@(cmdack==1);
@(posedge clk);
#1000;
cmd <= 3'b000;
end
endtask
// page_write_burst(address, start_value, data_mask, RCD, length)
//
// This task performs a page write burst access of size length
// at SDRAM address to the SDRAM controller
//
// address : Address in SDRAM to start the burst access
// start_value : Starting value for the burst write sequence. The write burst task
// simply increments the data values from the start_value.
// data_mask : Byte data mask for all cycles in the burst.
// RCD : RCD value that was set during configuration
// length : burst length of the access.
task page_write_burst;
input [`ASIZE-1 : 0] address;
input [`DSIZE-1 : 0] start_value;
input [`DSIZE/8-1 : 0] data_mask;
input [1 : 0] RCD;
input [15 : 0] length;
integer i;
begin
addr <= address;
cmd <= 3'b010;
datain <= start_value;
dm <= data_mask;
@(cmdack==1);
@(posedge clk);
#1000;
cmd <= 3'b000;
for (i=1 ; i<=(RCD-2); i=i+1)
@(posedge clk);
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