📄 ch9_2_2.rpt
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Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 13/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 3 0 8 0 1 1 1 1 1 8 1 0 8 0 0 0 0 0 0 0 0 0 0 0 33/0
B: 0 0 5 0 7 0 0 3 1 0 1 1 0 0 4 5 1 1 1 1 1 1 1 0 0 34/0
C: 7 0 0 0 1 3 7 1 1 6 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 27/0
Total: 7 3 5 8 8 4 8 5 3 7 9 3 0 8 4 5 1 1 1 1 1 1 1 0 0 94/0
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 CP
29 - - C -- INPUT 0 0 0 1 Din0
28 - - C -- INPUT 0 0 0 1 Din1
27 - - C -- INPUT 0 0 0 1 Din2
26 - - C -- INPUT 0 0 0 1 Din3
7 - - A -- INPUT 0 0 0 1 Din4
125 - - - -- INPUT 0 0 0 1 Din5
54 - - - -- INPUT 0 0 0 1 Din6
124 - - - -- INPUT 0 0 0 1 Din7
126 - - - -- INPUT 0 0 0 2 nINTR
56 - - - -- INPUT G 0 0 0 0 RST
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- OUTPUT 0 0 0 0 Dout0
80 - - C -- OUTPUT 0 1 0 0 Dout1
78 - - C -- OUTPUT 0 1 0 0 Dout2
79 - - C -- OUTPUT 0 1 0 0 Dout3
19 - - B -- OUTPUT 0 1 0 0 Dout4
20 - - B -- OUTPUT 0 1 0 0 Dout5
21 - - B -- OUTPUT 0 1 0 0 Dout6
22 - - B -- OUTPUT 0 1 0 0 Dout7
89 - - B -- OUTPUT 0 1 0 0 Dout8
88 - - B -- OUTPUT 0 1 0 0 Dout9
87 - - B -- OUTPUT 0 1 0 0 Dout10
12 - - A -- OUTPUT 0 0 0 0 Dout11
8 - - A -- OUTPUT 0 1 0 0 nCS
11 - - A -- OUTPUT 0 1 0 0 nRD
10 - - A -- OUTPUT 0 1 0 0 nWR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 07 OR2 s 0 4 0 1 |LPM_ADD_SUB:2115|addcore:adder|pcarry2~1
- 3 - C 01 AND2 0 3 0 2 |LPM_ADD_SUB:2115|addcore:adder|:53
- 6 - C 07 OR2 0 4 0 1 |LPM_ADD_SUB:2115|addcore:adder|:57
- 6 - C 01 OR2 0 3 0 4 |LPM_ADD_SUB:2115|addcore:adder|:70
- 7 - C 07 OR2 s 0 2 0 1 |LPM_ADD_SUB:2115|addcore:adder|~71~1
- 4 - C 07 OR2 0 4 0 3 |LPM_ADD_SUB:2115|addcore:adder|:71
- 3 - C 07 OR2 0 4 0 2 |LPM_ADD_SUB:2115|addcore:adder|:72
- 1 - B 08 OR2 0 4 0 2 |LPM_ADD_SUB:2166|addcore:adder|pcarry1
- 2 - B 08 AND2 0 2 0 1 |LPM_ADD_SUB:2166|addcore:adder|:53
- 3 - B 08 OR2 0 2 0 1 |LPM_ADD_SUB:2166|addcore:adder|:54
- 3 - B 05 OR2 0 4 0 1 |LPM_ADD_SUB:2166|addcore:adder|:59
- 1 - B 05 OR2 0 4 0 7 |LPM_ADD_SUB:2166|addcore:adder|:68
- 2 - B 05 OR2 0 4 0 4 |LPM_ADD_SUB:2166|addcore:adder|:69
- 1 - B 12 OR2 0 4 0 8 |LPM_ADD_SUB:2166|addcore:adder|:70
- 3 - B 14 OR2 0 2 0 1 |LPM_ADD_SUB:2445|addcore:adder|pcarry1
- 3 - B 15 OR2 0 4 0 1 |LPM_ADD_SUB:2445|addcore:adder|:69
- 1 - B 19 OR2 0 2 0 5 |LPM_ADD_SUB:2496|addcore:adder|:65
- 4 - B 15 OR2 0 4 0 1 |LPM_ADD_SUB:2497|addcore:adder|:59
- 6 - A 13 DFFE + 0 1 0 1 State~1
- 1 - A 13 DFFE + 1 1 0 4 State~2
- 7 - A 13 DFFE + 1 1 0 1 State~3
- 8 - A 13 DFFE + 0 1 0 5 State~4
- 2 - A 13 DFFE + ! 0 2 1 0 :23
- 4 - A 13 DFFE + ! 0 1 1 0 :25
- 5 - A 13 DFFE + ! 0 2 1 0 :27
- 3 - A 13 DFFE + 0 2 0 8 EC (:43)
- 1 - A 07 DFFE + 1 1 0 19 D7 (:44)
- 1 - A 02 DFFE + 1 1 0 19 D6 (:45)
- 2 - A 02 DFFE + 1 1 0 19 D5 (:46)
- 3 - A 02 DFFE + 1 1 0 17 D4 (:47)
- 1 - C 09 DFFE + 1 1 0 9 D3 (:48)
- 2 - C 06 DFFE + 1 1 0 9 D2 (:49)
- 1 - C 06 DFFE + 1 1 0 9 D1 (:50)
- 3 - C 06 DFFE + 1 1 0 5 D0 (:51)
- 4 - B 05 AND2 0 4 0 3 :580
- 6 - B 05 AND2 0 4 0 2 :589
- 8 - B 05 AND2 0 4 0 3 :598
- 1 - A 10 AND2 0 4 0 2 :607
- 8 - A 04 OR2 ! 0 4 0 3 :616
- 7 - A 04 OR2 ! 0 4 0 3 :625
- 1 - A 09 OR2 ! 0 4 0 3 :634
- 2 - A 12 AND2 0 4 0 3 :643
- 8 - A 11 AND2 0 4 0 2 :652
- 7 - A 11 OR2 ! 0 4 0 2 :661
- 1 - A 06 AND2 ! 0 2 0 4 :852
- 2 - B 03 OR2 0 4 0 2 :891
- 1 - B 03 OR2 0 4 0 3 :939
- 5 - B 05 OR2 s 0 4 0 1 ~998~1
- 3 - A 11 OR2 0 3 0 1 :1023
- 6 - A 11 OR2 s 0 4 0 1 ~1025~1
- 6 - A 04 OR2 s ! 0 2 0 2 ~1043~1
- 4 - A 04 OR2 0 4 0 2 :1043
- 5 - A 11 OR2 0 4 0 1 :1062
- 1 - A 11 OR2 0 3 0 1 :1068
- 5 - A 04 OR2 0 4 0 1 :1077
- 1 - A 04 AND2 0 4 0 3 :1094
- 3 - A 04 AND2 s 0 2 0 1 ~1130~1
- 6 - A 08 OR2 s 0 3 0 2 ~1142~1
- 1 - B 09 OR2 0 4 0 6 :1142
- 2 - B 11 OR2 0 4 0 1 :1190
- 4 - A 11 AND2 0 3 0 1 :1214
- 2 - A 11 OR2 s 0 4 0 1 ~1229~1
- 2 - A 04 OR2 0 4 0 2 :1230
- 2 - C 07 AND2 0 2 0 2 :1238
- 5 - C 10 OR2 ! 0 4 0 1 :1393
- 2 - C 10 OR2 0 3 0 3 :1851
- 6 - C 10 OR2 s 0 4 0 1 ~1881~1
- 1 - C 12 OR2 0 4 0 4 :1899
- 1 - C 05 AND2 s ! 0 3 0 4 ~1946~1
- 1 - C 07 OR2 0 4 0 1 :1949
- 3 - C 10 AND2 0 3 0 1 :1973
- 4 - C 10 OR2 s 0 3 0 2 ~1988~1
- 1 - C 10 OR2 0 4 0 3 :1988
- 2 - C 01 OR2 s 0 4 0 2 ~2045~1
- 2 - C 08 OR2 s 0 3 0 5 ~2045~2
- 1 - C 01 OR2 ! 0 3 0 7 :2118
- 2 - B 21 OR2 0 3 0 7 :2169
- 5 - C 01 OR2 0 4 1 0 :2370
- 7 - C 01 OR2 0 3 1 0 :2376
- 4 - C 01 OR2 0 2 1 0 :2382
- 1 - B 18 OR2 ! 0 2 0 3 :2415
- 1 - B 20 AND2 0 2 0 4 :2417
- 1 - B 22 OR2 ! 0 2 0 3 :2419
- 1 - B 15 OR2 0 4 0 1 :2535
- 2 - B 15 OR2 0 4 0 1 :2536
- 6 - B 15 OR2 0 4 1 0 :2540
- 2 - B 14 OR2 0 4 0 1 :2546
- 1 - B 14 OR2 0 4 0 1 :2549
- 5 - B 14 OR2 0 4 1 0 :2552
- 3 - B 16 OR2 0 4 1 0 :2564
- 3 - B 17 OR2 0 4 1 0 :2576
- 7 - B 03 OR2 0 4 1 0 :2734
- 6 - B 03 OR2 0 4 1 0 :2746
- 5 - B 03 OR2 0 3 1 0 :2758
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 13/ 48( 27%) 3/ 48( 6%) 1/16( 6%) 5/16( 31%) 0/16( 0%)
B: 7/ 96( 7%) 12/ 48( 25%) 8/ 48( 16%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 5/ 96( 5%) 17/ 48( 35%) 0/ 48( 0%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RST
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_2.rpt
ch9_2_2
** EQUATIONS **
CP : INPUT;
Din0 : INPUT;
Din1 : INPUT;
Din2 : INPUT;
Din3 : INPUT;
Din4 : INPUT;
Din5 : INPUT;
Din6 : INPUT;
Din7 : INPUT;
nINTR : INPUT;
RST : INPUT;
-- Node name is 'Dout0'
-- Equation name is 'Dout0', type is output
Dout0 = GND;
-- Node name is 'Dout1'
-- Equation name is 'Dout1', type is output
Dout1 = _LC4_C1;
-- Node name is 'Dout2'
-- Equation name is 'Dout2', type is output
Dout2 = _LC7_C1;
-- Node name is 'Dout3'
-- Equation name is 'Dout3', type is output
Dout3 = _LC5_C1;
-- Node name is 'Dout4'
-- Equation name is 'Dout4', type is output
Dout4 = _LC3_B17;
-- Node name is 'Dout5'
-- Equation name is 'Dout5', type is output
Dout5 = _LC3_B16;
-- Node name is 'Dout6'
-- Equation name is 'Dout6', type is output
Dout6 = _LC5_B14;
-- Node name is 'Dout7'
-- Equation name is 'Dout7', type is output
Dout7 = _LC6_B15;
-- Node name is 'Dout8'
-- Equation name is 'Dout8', type is output
Dout8 = _LC5_B3;
-- Node name is 'Dout9'
-- Equation name is 'Dout9', type is output
Dout9 = _LC6_B3;
-- Node name is 'Dout10'
-- Equation name is 'Dout10', type is output
Dout10 = _LC7_B3;
-- Node name is 'Dout11'
-- Equation name is 'Dout11', type is output
Dout11 = GND;
-- Node name is ':51' = 'D0'
-- Equation name is 'D0', location is LC3_C6, type is buried.
D0 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = D0 & !EC
# Din0 & EC;
-- Node name is ':50' = 'D1'
-- Equation name is 'D1', location is LC1_C6, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = D1 & !EC
# Din1 & EC;
-- Node name is ':49' = 'D2'
-- Equation name is 'D2', location is LC2_C6, type is buried.
D2 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = D2 & !EC
# Din2 & EC;
-- Node name is ':48' = 'D3'
-- Equation name is 'D3', location is LC1_C9, type is buried.
D3 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = D3 & !EC
# Din3 & EC;
-- Node name is ':47' = 'D4'
-- Equation name is 'D4', location is LC3_A2, type is buried.
D4 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
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