ch9_2_2.vhd

CH4CH2CH1VHDL 数字电路参考书所有程序9

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch9_2_2 is
	PORT(
		 Din		: IN	STD_LOGIC_VECTOR(7 Downto 0);	-- A/D Data
		 Dout		: OUT   STD_LOGIC_VECTOR(11 Downto 0);	-- BCD Out
		 CP			: IN    STD_LOGIC;		-- CLOCK
		 RST        : IN	STD_LOGIC;		-- System Reset
		 nCS,nWR,nRD: OUT   STD_LOGIC;		-- O/P Signal
		 nINTR		: IN    STD_LOGIC		-- I/P Signal	
		);
END Ch9_2_2;

--*********************************************
ARCHITECTURE a OF Ch9_2_2 IS

	TYPE 	STATE_TYPE IS	(S0,S1,S2,S3);	--State Type Declare
	SIGNAL  State 	: STATE_TYPE;		 	--State Signal Declare
	SIGNAL  EC,nIN	: STD_LOGIC;			--Synchronous Control & A/D nINTR 
	SIGNAL  D		: STD_LOGIC_VECTOR(7 Downto 0);	-- Read A/D Data 
	SIGNAL  Value   : STd_LOGIC_VECTOR(11 Downto 0);-- A/D Conversion Data	

BEGIN

SystemConnection: Block
Begin
	nIn <= nINTR;
	Dout <= Value;					-- BCD Number Display
End Block SystemConnection;


StateChange: Block					-- Signal Generator
Begin
	PROCESS (CP,RST)				
	BEGIN
		IF RST = '1' Then		--Reset State
				nCS <= '1';
				nWR <= '1';
				nRD <= '1';
				EC <= '0';

				State <= S0;

		ElsIF CP'Event And CP = '1' Then
			CASE State IS

				WHEN S0 =>				--STATE S0 & Write State
					nCS <= '0';
					nWR <= '0';
					nRD <= '1';
					EC <= '0';

					State <= S1;

				WHEN S1 =>				--STATE S1 & A/D Conversion State
					nCS <= '1';
					nWR <= '1';
					nRD <= '1';
					EC <= '0';
					
					If nIN = '0' Then		--nINTR = '0' ?
						State <= S2;
					End if;

				WHEN S2 =>				--STATE S2 & Read State
					nCS <= '0';
					nWR <= '1';
					nRD <= '0';
					EC <= '1';

					State <= S3;
			
				WHEN S3 =>				--STATE S3 
					nCS <= '1';
					nWR <= '1';
					nRD <= '1';
					EC <= '0';

					State <= S0;
					
				WHEN OTHERS =>			--Initial State	
					State <= S0;
					
	 			END CASE;
		ENd If;
	END PROCESS; 
End Block StateChange;


ReadData: Block
Begin
	PROCESS (CP)
	BEGIN 	
		IF CP'Event AND CP = '1' THEN
			IF EC = '1' THEN
				D <= Din ;				--Read A/D Convertor Data	
			END IF;
		END IF;
	END PROCESS;
End Block ReadData;


Conversion: Block
	Signal V : Std_Logic_Vector(7 downto 0);		--A/D Conversion Data
	Signal HB,LB : Std_Logic_Vector(11 downto 0);	 
	Signal C30,C74,C118 : Std_Logic;
	
Begin
	V <= D ;				-- A/D Data
								-- For A/D Conversion Data High Byte			
	HB <= "010010000000" When V(7 downto 4) = "1111" Else	--4.80
		  "010001001000" When V(7 downto 4) = "1110" Else	--4.48
		  "010000010110" When V(7 downto 4) = "1101" Else	--4.16	
		  "001110000100" When V(7 downto 4) = "1100" Else	--3.84
          "001101010010" When V(7 downto 4) = "1011" Else	--3.52
   		  "001100100000" When V(7 downto 4) = "1010" Else	--3.20
   		  "001010001000" When V(7 downto 4) = "1001" Else	--2.88	
		  "001001010110" When V(7 downto 4) = "1000" Else	--2.56
	 	  "001000100100" When V(7 downto 4) = "0111" Else	--2.24
		  "000110010010" When V(7 downto 4) = "0110" Else	--1.92
		  "000101100000" When V(7 downto 4) = "0101" Else	--1.60
		  "000100101000" When V(7 downto 4) = "0100" Else	--1.28
		  "000010010110" When V(7 downto 4) = "0011" Else	--0.96
		  "000001100100" When V(7 downto 4) = "0010" Else	--0.64
		  "000000110010" When V(7 downto 4) = "0001" Else	--0.32
		  "000000000000";									--0.00

		 							--For A/D Conversion Data Low Byte
	LB <= "000000110000" When V(3 downto 0) = "1111" Else	--0.30
		  "000000101000" When V(3 downto 0) = "1110" Else	--0.28
		  "000000100110" When V(3 downto 0) = "1101" Else	--0.26
		  "000000100100" When V(3 downto 0) = "1100" Else	--0.24
    	  "000000100010" When V(3 downto 0) = "1011" Else	--0.22
   		  "000000100000" When V(3 downto 0) = "1010" Else	--0.20
   		  "000000011000" When V(3 downto 0) = "1001" Else	--0.18	
		  "000000010110" When V(3 downto 0) = "1000" Else	--0.16
	 	  "000000010100" When V(3 downto 0) = "0111" Else	--0.14
		  "000000010010" When V(3 downto 0) = "0110" Else	--0.12
		  "000000010000" When V(3 downto 0) = "0101" Else	--0.10
		  "000000001000" When V(3 downto 0) = "0100" Else	--0.08
		  "000000000110" When V(3 downto 0) = "0011" Else	--0.06
		  "000000000100" When V(3 downto 0) = "0010" Else	--0.04
		  "000000000010" When V(3 downto 0) = "0001" Else	--0.02
		  "000000000000";									--0.00

		  							--Check BCD Addition Carry
	C30 <= '1' When HB(3 Downto 0) + LB(3 Downto 0) > "1001" Else
		   '0';	
	C74 <= '1' When HB(7 Downto 4) + LB(7 Downto 4) > "1001" Else
		   '0';	
	C118 <= '1' When HB(11 Downto 8) + LB(11 Downto 8) > "1001" Else
		    '0';	

									-- BCD Addition (3~0)					
	Value(3 Downto 0) <= HB(3 Downto 0) + LB(3 Downto 0) + "0110" When C30 ='1' Else
						 HB(3 Downto 0) + LB(3 Downto 0);
									-- BCD Addition (7~4)
	Value(7 Downto 4) <= HB(7 Downto 4) + LB(7 Downto 4) + "0111" When C74 ='1' And C30 = '1' Else
						 HB(7 Downto 4) + LB(7 Downto 4) + "0110" When C74 ='1' And C30 = '0' Else
						 HB(7 Downto 4) + LB(7 Downto 4) + "0001" When C74 ='0' And C30 = '1' Else
						 HB(7 Downto 4) + LB(7 Downto 4);
									-- BCD Addition (11~8)
	Value(11 Downto 8) <= HB(11 Downto 8) + LB(11 Downto 8) + "0111" When C118 ='1' And C74 = '1' Else
						  HB(11 Downto 8) + LB(11 Downto 8) + "0110" When C118 ='1' And C74 = '0' Else
						  HB(11 Downto 8) + LB(11 Downto 8) + "0001" When C118 ='0' And C74 = '1' Else
						  HB(11 Downto 8) + LB(11 Downto 8);

End Block Conversion;



END a;