📄 ch9_2_3.rpt
字号:
SEGOUT4 | 29 80 | RESERVED
SEGOUT5 | 30 79 | RESERVED
SEGOUT6 | 31 78 | RESERVED
SEGOUT7 | 32 77 | ^MSEL0
SELOUT0 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
SELOUT1 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
S n R G R R R R V R R R R G R V V G C G G G R R V R R R R G R R R R V R
E C E N E E E E C E E E E N E C C N P N N N E E C E E E E N E E E E C E
L S S D S S S S C S S S S D S C C D D D D S S C S S S S D S S S S C S
O E I E E E E I E E E E I E I I I I I I E E I E E E E I E E E E I E
U R O R R R R O R R R R O R N N N N N N R R O R R R R O R R R R O R
T V V V V V V V V V V T T T T T T V V V V V V V V V V V
2 E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A2 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 13/22( 59%)
A3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A7 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 11/22( 50%)
A8 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
A9 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A10 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
A11 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A12 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A13 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
A14 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A16 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
A20 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
A21 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
A22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
A24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B1 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B4 2/ 8( 25%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
B5 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
B6 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
B7 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B9 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B11 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
B23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B24 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C3 6/ 8( 75%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
C4 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C5 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
C6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C10 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C17 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C18 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C20 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C22 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
C23 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C24 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 27/96 ( 28%)
Total logic cells used: 174/576 ( 30%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 587/2304 ( 25%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 18
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 174
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 23/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 1 8 1 1 1 1 6 2 1 4 3 1 0 3 8 1 1 1 0 0 8 5 1 0 1 59/0
B: 3 1 1 2 7 7 7 1 5 1 1 1 0 8 0 0 0 0 1 1 1 1 8 1 3 61/0
C: 1 1 6 3 5 2 1 1 1 3 1 1 0 0 1 1 1 1 1 1 6 1 7 3 5 54/0
Total: 5 10 8 6 13 10 14 4 7 8 5 3 0 11 9 2 2 2 2 2 15 7 16 4 9 174/0
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 CP
131 - - - 15 INPUT 0 0 0 1 Din0
132 - - - 16 INPUT 0 0 0 1 Din1
133 - - - 17 INPUT 0 0 0 1 Din2
135 - - - 18 INPUT 0 0 0 1 Din3
136 - - - 19 INPUT 0 0 0 1 Din4
137 - - - 19 INPUT 0 0 0 1 Din5
138 - - - 20 INPUT 0 0 0 1 Din6
140 - - - 21 INPUT 0 0 0 1 Din7
143 - - - 24 INPUT 0 0 0 2 nINTR
124 - - - -- INPUT G 0 0 0 0 RST
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - C -- OUTPUT 0 1 0 0 Dout0
81 - - C -- OUTPUT 0 1 0 0 Dout1
82 - - C -- OUTPUT 0 1 0 0 Dout2
111 - - - 02 OUTPUT 0 1 0 0 Dout3
38 - - - 22 OUTPUT 0 1 0 0 nCS
128 - - - 13 OUTPUT 0 1 0 0 nRD
11 - - A -- OUTPUT 0 1 0 0 nWR
23 - - B -- OUTPUT 0 1 0 0 SEGOUT0
26 - - C -- OUTPUT 0 1 0 0 SEGOUT1
27 - - C -- OUTPUT 0 1 0 0 SEGOUT2
28 - - C -- OUTPUT 0 1 0 0 SEGOUT3
29 - - C -- OUTPUT 0 1 0 0 SEGOUT4
30 - - C -- OUTPUT 0 1 0 0 SEGOUT5
31 - - C -- OUTPUT 0 1 0 0 SEGOUT6
32 - - C -- OUTPUT 0 1 0 0 SEGOUT7
33 - - C -- OUTPUT 0 1 0 0 SELOUT0
36 - - - 24 OUTPUT 0 1 0 0 SELOUT1
37 - - - 23 OUTPUT 0 1 0 0 SELOUT2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch9\ch9_2_3.rpt
ch9_2_3
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 20 AND2 0 3 0 4 |LPM_ADD_SUB:504|addcore:adder|:107
- 2 - A 20 AND2 0 4 0 4 |LPM_ADD_SUB:504|addcore:adder|:119
- 4 - A 21 AND2 0 4 0 4 |LPM_ADD_SUB:504|addcore:adder|:131
- 7 - A 14 AND2 0 4 0 4 |LPM_ADD_SUB:504|addcore:adder|:143
- 8 - A 14 AND2 0 2 0 1 |LPM_ADD_SUB:504|addcore:adder|:147
- 1 - B 13 OR2 0 4 0 3 |LPM_ADD_SUB:2304|addcore:adder|:72
- 2 - B 07 OR2 0 4 0 4 |LPM_ADD_SUB:2355|addcore:adder|:69
- 6 - B 13 OR2 s 0 4 0 1 |LPM_ADD_SUB:2527|addcore:adder|pcarry2~1
- 7 - B 13 OR2 0 4 0 2 |LPM_ADD_SUB:2527|addcore:adder|:53
- 8 - B 13 AND2 0 3 0 1 |LPM_ADD_SUB:2527|addcore:adder|:57
- 3 - B 13 OR2 0 4 0 4 |LPM_ADD_SUB:2527|addcore:adder|:70
- 2 - B 13 OR2 0 4 0 3 |LPM_ADD_SUB:2527|addcore:adder|:71
- 4 - B 07 OR2 0 4 0 2 |LPM_ADD_SUB:2633|addcore:adder|pcarry1
- 4 - B 22 OR2 0 4 0 2 |LPM_ADD_SUB:2633|addcore:adder|:48
- 3 - B 07 OR2 0 4 0 1 |LPM_ADD_SUB:2633|addcore:adder|:59
- 1 - B 07 OR2 0 4 0 7 |LPM_ADD_SUB:2633|addcore:adder|:68
- 3 - B 03 OR2 0 4 0 6 |LPM_ADD_SUB:2633|addcore:adder|:70
- 7 - B 06 OR2 0 2 0 2 |LPM_ADD_SUB:2634|addcore:adder|pcarry1
- 6 - B 06 OR2 0 3 0 1 |LPM_ADD_SUB:2660|addcore:adder|:69
- 2 - B 22 OR2 0 4 0 4 |LPM_ADD_SUB:2685|addcore:adder|:65
- 3 - B 09 AND2 0 2 0 2 |LPM_ADD_SUB:2686|addcore:adder|:55
- 3 - A 13 DFFE + 0 1 0 1 State~1
- 2 - A 22 DFFE + 1 1 0 4 State~2
- 1 - A 17 DFFE + 1 1 0 4 State~3
- 2 - A 13 DFFE + 0 1 0 5 State~4
- 1 - A 21 DFFE + ! 0 3 1 0 :26
- 5 - A 15 DFFE + ! 0 1 1 0 :28
- 1 - A 13 DFFE + ! 0 3 1 0 :30
- 2 - A 16 DFFE + 0 3 0 8 EC (:63)
- 2 - A 08 DFFE + 1 1 0 15 D7 (:64)
- 1 - B 11 DFFE + 1 1 0 15 D6 (:65)
- 1 - A 12 DFFE + 1 1 0 20 D5 (:66)
- 1 - A 09 DFFE + 1 1 0 19 D4 (:67)
- 4 - B 18 DFFE + 1 1 0 9 D3 (:68)
- 4 - B 24 DFFE + 1 1 0 9 D2 (:69)
- 5 - B 24 DFFE + 1 1 0 9 D1 (:70)
- 8 - B 24 DFFE + 1 1 0 7 D0 (:71)
- 4 - A 14 DFFE + 0 3 0 10 Q15 (:155)
- 2 - A 14 DFFE + 0 3 0 12 Q14 (:156)
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