counter.fit.qmsg

4X4 KEYPAD 的输入位数计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 31 16:04:38 2004 " "Info: Processing started: Sun Oct 31 16:04:38 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off counter -c counter " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off counter -c counter" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "counter EP20K200EFC484-2X " "Info: Selected device EP20K200EFC484-2X for design counter" {  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "SignalProbe " "Warning: Feature SignalProbe is not available with your current license" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell clk to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Sun Oct 31 2004 16:04:40 " "Info: Started fitting attempt 1 on Sun Oct 31 2004 at 16:04:40" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "2 " "Info: Maximum row FastTrack interconnect = 2%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.264 ns register register " "Info: Estimated most critical path is register to register delay of 3.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns mod10\[0\] 1 REG LAB_6_I1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LAB_6_I1; Fanout = 6; REG Node = 'mod10\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { mod10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.899 ns) 1.392 ns process0~34 2 COMB LAB_6_I1 1 " "Info: 2: + IC(0.284 ns) + CELL(0.899 ns) = 1.392 ns; Loc. = LAB_6_I1; Fanout = 1; COMB Node = 'process0~34'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.183 ns" { mod10[0] process0~34 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.689 ns) 2.081 ns process0~36 3 COMB LAB_6_I1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.689 ns) = 2.081 ns; Loc. = LAB_6_I1; Fanout = 2; COMB Node = 'process0~36'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "0.689 ns" { process0~34 process0~36 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.899 ns) 3.264 ns mod1\[3\] 4 REG LAB_6_I1 4 " "Info: 4: + IC(0.284 ns) + CELL(0.899 ns) = 3.264 ns; Loc. = LAB_6_I1; Fanout = 4; REG Node = 'mod1\[3\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.183 ns" { process0~36 mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.696 ns 82.60 % " "Info: Total cell delay = 2.696 ns ( 82.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.568 ns 17.40 % " "Info: Total interconnect delay = 0.568 ns ( 17.40 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "3.264 ns" { mod10[0] process0~34 process0~36 mod1[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "5 " "Info: Fitter routing operations ending: elapsed time = 5 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 31 16:04:47 2004 " "Info: Processing ended: Sun Oct 31 16:04:47 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}