counter.tan.qmsg

4X4 KEYPAD 的输入位数计数器

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dout1\[2\] mod1\[2\] 7.192 ns register " "Info: Minimum tco from clock clk to destination pin dout1\[2\] through register mod1\[2\] is 7.192 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod1\[2\] 2 REG LC8_7_I1 5 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.020 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.020 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns mod1\[2\] 1 REG LC8_7_I1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(2.566 ns) 4.020 ns dout1\[2\] 2 PIN PIN_H1 0 " "Info: 2: + IC(1.245 ns) + CELL(2.566 ns) = 4.020 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'dout1\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "3.811 ns" { mod1[2] dout1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.775 ns 69.03 % " "Info: Total cell delay = 2.775 ns ( 69.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.245 ns 30.97 % " "Info: Total interconnect delay = 1.245 ns ( 30.97 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "4.020 ns" { mod1[2] dout1[2] } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "4.020 ns" { mod1[2] dout1[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 31 16:04:54 2004 " "Info: Processing ended: Sun Oct 31 16:04:54 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}