📄 counter.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } { "c:/altera/quartus41sp2/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register mod1\[0\] mod1\[3\] 233.64 MHz Internal " "Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register mod1\[0\] and destination register mod1\[3\]" { { "Info" "ITDB_CLOCK_RATE" "clock 4.28 ns " "Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.544 ns + Longest register register " "Info: + Longest register to register delay is 3.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns mod1\[0\] 1 REG LC9_7_I1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC9_7_I1; Fanout = 7; REG Node = 'mod1\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { mod1[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(1.034 ns) 2.471 ns add~17 2 COMB LC10_6_I1 1 " "Info: 2: + IC(1.228 ns) + CELL(1.034 ns) = 2.471 ns; Loc. = LC10_6_I1; Fanout = 1; COMB Node = 'add~17'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.262 ns" { mod1[0] add~17 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.789 ns) 3.544 ns mod1\[3\] 3 REG LC4_6_I1 4 " "Info: 3: + IC(0.284 ns) + CELL(0.789 ns) = 3.544 ns; Loc. = LC4_6_I1; Fanout = 4; REG Node = 'mod1\[3\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.073 ns" { add~17 mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.032 ns 57.34 % " "Info: Total cell delay = 2.032 ns ( 57.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.512 ns 42.66 % " "Info: Total interconnect delay = 1.512 ns ( 42.66 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "3.544 ns" { mod1[0] add~17 mod1[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod1\[3\] 2 REG LC4_6_I1 4 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC4_6_I1; Fanout = 4; REG Node = 'mod1\[3\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod1\[0\] 2 REG LC9_7_I1 7 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC9_7_I1; Fanout = 7; REG Node = 'mod1\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod1[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "3.544 ns" { mod1[0] add~17 mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { mod1[3] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "mod1\[2\] counter_clear clk 5.125 ns register " "Info: tsu for register mod1\[2\] (data pin = counter_clear, clock pin = clk) is 5.125 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.699 ns + Longest pin register " "Info: + Longest pin to register delay is 7.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns counter_clear 1 PIN PIN_G22 8 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_G22; Fanout = 8; PIN Node = 'counter_clear'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { counter_clear } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.084 ns) + CELL(0.869 ns) 7.699 ns mod1\[2\] 2 REG LC8_7_I1 5 " "Info: 2: + IC(5.084 ns) + CELL(0.869 ns) = 7.699 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1\[2\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "5.953 ns" { counter_clear mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.615 ns 33.97 % " "Info: Total cell delay = 2.615 ns ( 33.97 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.084 ns 66.03 % " "Info: Total interconnect delay = 5.084 ns ( 66.03 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "7.699 ns" { counter_clear mod1[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod1\[2\] 2 REG LC8_7_I1 5 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1\[2\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[2] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "7.699 ns" { counter_clear mod1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod1[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout10\[1\] mod10\[1\] 8.958 ns register " "Info: tco from clock clk to destination pin dout10\[1\] through register mod10\[1\] is 8.958 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod10\[1\] 2 REG LC10_7_I1 5 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC10_7_I1; Fanout = 5; REG Node = 'mod10\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod10[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.786 ns + Longest register pin " "Info: + Longest register to pin delay is 5.786 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns mod10\[1\] 1 REG LC10_7_I1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_7_I1; Fanout = 5; REG Node = 'mod10\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { mod10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.011 ns) + CELL(2.566 ns) 5.786 ns dout10\[1\] 2 PIN PIN_H19 0 " "Info: 2: + IC(3.011 ns) + CELL(2.566 ns) = 5.786 ns; Loc. = PIN_H19; Fanout = 0; PIN Node = 'dout10\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "5.577 ns" { mod10[1] dout10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.775 ns 47.96 % " "Info: Total cell delay = 2.775 ns ( 47.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.011 ns 52.04 % " "Info: Total interconnect delay = 3.011 ns ( 52.04 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "5.786 ns" { mod10[1] dout10[1] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "5.786 ns" { mod10[1] dout10[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "mod10\[0\] counter_clear clk -4.488 ns register " "Info: th for register mod10\[0\] (data pin = counter_clear, clock pin = clk) is -4.488 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.000 ns) 2.738 ns mod10\[0\] 2 REG LC6_6_I1 6 " "Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC6_6_I1; Fanout = 6; REG Node = 'mod10\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "1.365 ns" { clk mod10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.15 % " "Info: Total cell delay = 1.373 ns ( 50.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.365 ns 49.85 % " "Info: Total interconnect delay = 1.365 ns ( 49.85 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod10[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.349 ns + " "Info: + Micro hold delay of destination is 0.349 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.575 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns counter_clear 1 PIN PIN_G22 8 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_G22; Fanout = 8; PIN Node = 'counter_clear'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "" { counter_clear } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.040 ns) + CELL(0.789 ns) 7.575 ns mod10\[0\] 2 REG LC6_6_I1 6 " "Info: 2: + IC(5.040 ns) + CELL(0.789 ns) = 7.575 ns; Loc. = LC6_6_I1; Fanout = 6; REG Node = 'mod10\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "5.829 ns" { counter_clear mod10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/counter.vhd" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.535 ns 33.47 % " "Info: Total cell delay = 2.535 ns ( 33.47 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.040 ns 66.53 % " "Info: Total interconnect delay = 5.040 ns ( 66.53 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "7.575 ns" { counter_clear mod10[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "2.738 ns" { clk mod10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/counter/db/counter.quartus_db" { Floorplan "" "" "7.575 ns" { counter_clear mod10[0] } "NODE_NAME" } } } } 0}
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