counter.tan.rpt

4X4 KEYPAD 的输入位数计数器

; Slack ; Required tsu ; Actual tsu ; From          ; To       ; To Clock ;
+-------+--------------+------------+---------------+----------+----------+
; N/A   ; None         ; 5.125 ns   ; counter_clear ; mod1[2]  ; clk      ;
; N/A   ; None         ; 5.125 ns   ; counter_clear ; mod1[0]  ; clk      ;
; N/A   ; None         ; 5.124 ns   ; counter_clear ; mod10[1] ; clk      ;
; N/A   ; None         ; 5.109 ns   ; counter_clear ; mod1[1]  ; clk      ;
; N/A   ; None         ; 5.072 ns   ; counter_clear ; mod10[3] ; clk      ;
; N/A   ; None         ; 5.062 ns   ; counter_clear ; mod1[3]  ; clk      ;
; N/A   ; None         ; 5.005 ns   ; counter_clear ; mod10[2] ; clk      ;
; N/A   ; None         ; 5.001 ns   ; counter_clear ; mod10[0] ; clk      ;
+-------+--------------+------------+---------------+----------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+----------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To        ; From Clock ;
+-------+--------------+------------+----------+-----------+------------+
; N/A   ; None         ; 8.958 ns   ; mod10[1] ; dout10[1] ; clk        ;
; N/A   ; None         ; 8.517 ns   ; mod10[0] ; dout10[0] ; clk        ;
; N/A   ; None         ; 8.511 ns   ; mod10[2] ; dout10[2] ; clk        ;
; N/A   ; None         ; 8.404 ns   ; mod10[3] ; dout10[3] ; clk        ;
; N/A   ; None         ; 7.209 ns   ; mod1[0]  ; dout1[0]  ; clk        ;
; N/A   ; None         ; 7.198 ns   ; mod1[1]  ; dout1[1]  ; clk        ;
; N/A   ; None         ; 7.196 ns   ; mod1[3]  ; dout1[3]  ; clk        ;
; N/A   ; None         ; 7.192 ns   ; mod1[2]  ; dout1[2]  ; clk        ;
+-------+--------------+------------+----------+-----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+---------------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From          ; To       ; To Clock ;
+---------------+-------------+-----------+---------------+----------+----------+
; N/A           ; None        ; -4.488 ns ; counter_clear ; mod10[0] ; clk      ;
; N/A           ; None        ; -4.492 ns ; counter_clear ; mod10[2] ; clk      ;
; N/A           ; None        ; -4.549 ns ; counter_clear ; mod1[3]  ; clk      ;
; N/A           ; None        ; -4.559 ns ; counter_clear ; mod10[3] ; clk      ;
; N/A           ; None        ; -4.596 ns ; counter_clear ; mod1[1]  ; clk      ;
; N/A           ; None        ; -4.611 ns ; counter_clear ; mod10[1] ; clk      ;
; N/A           ; None        ; -4.612 ns ; counter_clear ; mod1[2]  ; clk      ;
; N/A           ; None        ; -4.612 ns ; counter_clear ; mod1[0]  ; clk      ;
+---------------+-------------+-----------+---------------+----------+----------+


+---------------------------------------------------------------------------------------+
; Minimum tco                                                                           ;
+---------------+------------------+----------------+----------+-----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From     ; To        ; From Clock ;
+---------------+------------------+----------------+----------+-----------+------------+
; N/A           ; None             ; 7.192 ns       ; mod1[2]  ; dout1[2]  ; clk        ;
; N/A           ; None             ; 7.196 ns       ; mod1[3]  ; dout1[3]  ; clk        ;
; N/A           ; None             ; 7.198 ns       ; mod1[1]  ; dout1[1]  ; clk        ;
; N/A           ; None             ; 7.209 ns       ; mod1[0]  ; dout1[0]  ; clk        ;
; N/A           ; None             ; 8.404 ns       ; mod10[3] ; dout10[3] ; clk        ;
; N/A           ; None             ; 8.511 ns       ; mod10[2] ; dout10[2] ; clk        ;
; N/A           ; None             ; 8.517 ns       ; mod10[0] ; dout10[0] ; clk        ;
; N/A           ; None             ; 8.958 ns       ; mod10[1] ; dout10[1] ; clk        ;
+---------------+------------------+----------------+----------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Oct 31 16:04:52 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter -c counter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register mod1[0] and destination register mod1[3]
    Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.544 ns
            Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC9_7_I1; Fanout = 7; REG Node = 'mod1[0]'
            Info: 2: + IC(1.228 ns) + CELL(1.034 ns) = 2.471 ns; Loc. = LC10_6_I1; Fanout = 1; COMB Node = 'add~17'
            Info: 3: + IC(0.284 ns) + CELL(0.789 ns) = 3.544 ns; Loc. = LC4_6_I1; Fanout = 4; REG Node = 'mod1[3]'
            Info: Total cell delay = 2.032 ns ( 57.34 % )
            Info: Total interconnect delay = 1.512 ns ( 42.66 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC4_6_I1; Fanout = 4; REG Node = 'mod1[3]'
                Info: Total cell delay = 1.373 ns ( 50.15 % )
                Info: Total interconnect delay = 1.365 ns ( 49.85 % )
            Info: - Longest clock path from clock clk to source register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC9_7_I1; Fanout = 7; REG Node = 'mod1[0]'
                Info: Total cell delay = 1.373 ns ( 50.15 % )
                Info: Total interconnect delay = 1.365 ns ( 49.85 % )
        Info: + Micro clock to output delay of source is 0.434 ns
        Info: + Micro setup delay of destination is 0.164 ns
Info: tsu for register mod1[2] (data pin = counter_clear, clock pin = clk) is 5.125 ns
    Info: + Longest pin to register delay is 7.699 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_G22; Fanout = 8; PIN Node = 'counter_clear'
        Info: 2: + IC(5.084 ns) + CELL(0.869 ns) = 7.699 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1[2]'
        Info: Total cell delay = 2.615 ns ( 33.97 % )
        Info: Total interconnect delay = 5.084 ns ( 66.03 % )
    Info: + Micro setup delay of destination is 0.164 ns
    Info: - Shortest clock path from clock clk to destination register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1[2]'
        Info: Total cell delay = 1.373 ns ( 50.15 % )
        Info: Total interconnect delay = 1.365 ns ( 49.85 % )
Info: tco from clock clk to destination pin dout10[1] through register mod10[1] is 8.958 ns
    Info: + Longest clock path from clock clk to source register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC10_7_I1; Fanout = 5; REG Node = 'mod10[1]'
        Info: Total cell delay = 1.373 ns ( 50.15 % )
        Info: Total interconnect delay = 1.365 ns ( 49.85 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Longest register to pin delay is 5.786 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_7_I1; Fanout = 5; REG Node = 'mod10[1]'
        Info: 2: + IC(3.011 ns) + CELL(2.566 ns) = 5.786 ns; Loc. = PIN_H19; Fanout = 0; PIN Node = 'dout10[1]'
        Info: Total cell delay = 2.775 ns ( 47.96 % )
        Info: Total interconnect delay = 3.011 ns ( 52.04 % )
Info: th for register mod10[0] (data pin = counter_clear, clock pin = clk) is -4.488 ns
    Info: + Longest clock path from clock clk to destination register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC6_6_I1; Fanout = 6; REG Node = 'mod10[0]'
        Info: Total cell delay = 1.373 ns ( 50.15 % )
        Info: Total interconnect delay = 1.365 ns ( 49.85 % )
    Info: + Micro hold delay of destination is 0.349 ns
    Info: - Shortest pin to register delay is 7.575 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_G22; Fanout = 8; PIN Node = 'counter_clear'
        Info: 2: + IC(5.040 ns) + CELL(0.789 ns) = 7.575 ns; Loc. = LC6_6_I1; Fanout = 6; REG Node = 'mod10[0]'
        Info: Total cell delay = 2.535 ns ( 33.47 % )
        Info: Total interconnect delay = 5.040 ns ( 66.53 % )
Info: Minimum tco from clock clk to destination pin dout1[2] through register mod1[2] is 7.192 ns
    Info: + Shortest clock path from clock clk to source register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.365 ns) + CELL(0.000 ns) = 2.738 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1[2]'
        Info: Total cell delay = 1.373 ns ( 50.15 % )
        Info: Total interconnect delay = 1.365 ns ( 49.85 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Shortest register to pin delay is 4.020 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC8_7_I1; Fanout = 5; REG Node = 'mod1[2]'
        Info: 2: + IC(1.245 ns) + CELL(2.566 ns) = 4.020 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'dout1[2]'
        Info: Total cell delay = 2.775 ns ( 69.03 % )
        Info: Total interconnect delay = 1.245 ns ( 30.97 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 31 16:04:54 2004
    Info: Elapsed time: 00:00:02