📄 counter.tan.rpt
字号:
Timing Analyzer report for counter
Sun Oct 31 16:04:54 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Minimum tco
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP20K200EFC484-2X ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.125 ns ; counter_clear ; mod1[0] ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.958 ns ; mod10[1] ; dout10[1] ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -4.488 ns ; counter_clear ; mod10[0] ; ; clk ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 7.192 ns ; mod1[2] ; dout1[2] ; clk ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod1[3] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-----------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[1] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[2] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[2] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[2] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[1] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[1] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[3] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[3] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod1[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[0] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[0] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod1[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[3] ; mod1[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[0] ; mod10[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[0] ; mod1[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[1] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod1[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[2] ; mod1[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[2] ; mod10[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[1] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[3] ; mod10[3] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[1] ; mod1[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod10[0] ; mod10[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod1[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; mod1[0] ; mod1[2] ; clk ; clk ; None ; None ; None ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+---------------+----------+----------+
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -