counter.vhd

4X4 KEYPAD 的输入位数计数器

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-- Copyright (C) 1991-2004 Altera Corporation
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-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sat Oct 23 04:55:36 2004

-- counter will count a decimal number from 1 to 77;
-- it output two digits of the number from 0 to 9 ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter IS
	PORT
	(
	 signal clk: in std_logic;
	 signal counter_clear: in std_logic;
	 signal dout1: out integer range 0 to 9; -- low digit
	 signal dout10: out integer range 0 to 9 -- high digit
	);
END counter;

ARCHITECTURE counter_architecture OF counter IS
begin
  process(clk)
      variable mod1: integer range 0 to 9;
      variable mod10: integer range 0 to 9;
  begin
  if (clk'event and clk='1') then
     if counter_clear='1' then -- count when counter_clear is high
          if mod1=9 then
               mod1:=0;
               mod10:=mod10+1;
          elsif (mod10=7 and mod1=7) then
                        mod1:=1;
                        mod10:=0;  -- count 01 after 77;
          else
                        mod1:=mod1+1;
          end if;
      elsif counter_clear='0' then -- reset when counter_clear is low
          mod1:=1;
          mod10:=0;
      end if;
   end if;
   dout1 <= mod1;
   dout10 <= mod10;
end process;
END counter_architecture;