counter_clear.vhd

4X4 KEYPAD 的输入位数计数器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sat Oct 23 21:51:27 2004

-- counter_clear is used to determine the state of counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter_clear IS
	PORT
	(
	 signal counter_clear: out std_logic;
	 signal count,clear,clk: in std_logic
	);
END counter_clear;

ARCHITECTURE counter_clear_architecture OF counter_clear IS
signal temp: std_logic;
BEGIN
process(count,clear,clk,temp)
begin
     if (clk'event and clk='1') then
        if(count='0' and clear='1') then
            temp<='1';
        end if;
        if (clear='0' and count='1') then
            temp<='0';
        end if;
     end if;
        counter_clear <= temp;  -- counter will count when counter_clear 
                                -- is high, and clear if counter_clear is low.

end process;
END counter_clear_architecture;