reg_comp.tan.qmsg

4X4 KEYPAD 的密码比较模块

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk result result~reg0 5.627 ns register " "Info: Minimum tco from clock clk to destination pin result through register result~reg0 is 5.627 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.663 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns result~reg0 2 REG LC2_6_E1 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk result~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.629 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns result~reg0 1 REG LC2_6_E1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(2.410 ns) 3.629 ns result 2 PIN PIN_79 0 " "Info: 2: + IC(1.058 ns) + CELL(2.410 ns) = 3.629 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'result'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "3.468 ns" { result~reg0 result } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns 70.85 % " "Info: Total cell delay = 2.571 ns ( 70.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns 29.15 % " "Info: Total interconnect delay = 1.058 ns ( 29.15 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "3.629 ns" { result~reg0 result } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "3.629 ns" { result~reg0 result } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 31 05:27:41 2004 " "Info: Processing ended: Sun Oct 31 05:27:41 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}