📄 reg_comp.tan.rpt
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Timing Analyzer report for reg_comp
Sun Oct 31 05:27:41 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Minimum tco
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP20K30ETC144-1 ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.969 ns ; RE ; dout1[1]~reg0 ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.859 ns ; dout10[0]~reg0 ; dout10[0] ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -3.012 ns ; din10[0] ; dout10[0]~reg0 ; ; clk ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 5.627 ns ; result~reg0 ; result ; clk ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout1[0]~reg0 ; result~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------------+----------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout1[0]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout10[2]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout10[0]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout10[3]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout1[2]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout1[1]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout1[3]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; dout10[1]~reg0 ; result~reg0 ; clk ; clk ; None ; None ; None ;
+-------+------------------------------------------------+----------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-----------+----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-----------+----------------+----------+
; N/A ; None ; 5.969 ns ; RE ; dout10[3]~reg0 ; clk ;
; N/A ; None ; 5.969 ns ; RE ; dout1[1]~reg0 ; clk ;
; N/A ; None ; 5.968 ns ; RE ; dout10[1]~reg0 ; clk ;
; N/A ; None ; 5.968 ns ; RE ; dout10[0]~reg0 ; clk ;
; N/A ; None ; 5.967 ns ; RE ; dout1[0]~reg0 ; clk ;
; N/A ; None ; 5.961 ns ; RE ; dout1[3]~reg0 ; clk ;
; N/A ; None ; 5.861 ns ; read_comp ; dout10[3]~reg0 ; clk ;
; N/A ; None ; 5.861 ns ; read_comp ; dout1[1]~reg0 ; clk ;
; N/A ; None ; 5.860 ns ; read_comp ; dout10[1]~reg0 ; clk ;
; N/A ; None ; 5.860 ns ; read_comp ; dout10[0]~reg0 ; clk ;
; N/A ; None ; 5.859 ns ; read_comp ; dout1[0]~reg0 ; clk ;
; N/A ; None ; 5.853 ns ; read_comp ; dout1[3]~reg0 ; clk ;
; N/A ; None ; 5.321 ns ; din1[2] ; result~reg0 ; clk ;
; N/A ; None ; 5.307 ns ; din10[2] ; result~reg0 ; clk ;
; N/A ; None ; 5.257 ns ; din1[0] ; result~reg0 ; clk ;
; N/A ; None ; 5.234 ns ; din10[3] ; result~reg0 ; clk ;
; N/A ; None ; 5.195 ns ; din1[1] ; result~reg0 ; clk ;
; N/A ; None ; 5.184 ns ; RE ; dout10[2]~reg0 ; clk ;
; N/A ; None ; 5.184 ns ; RE ; dout1[2]~reg0 ; clk ;
; N/A ; None ; 5.124 ns ; din10[0] ; result~reg0 ; clk ;
; N/A ; None ; 5.076 ns ; read_comp ; dout10[2]~reg0 ; clk ;
; N/A ; None ; 5.076 ns ; read_comp ; dout1[2]~reg0 ; clk ;
; N/A ; None ; 4.699 ns ; din10[1] ; result~reg0 ; clk ;
; N/A ; None ; 4.642 ns ; din1[3] ; result~reg0 ; clk ;
; N/A ; None ; 4.155 ns ; din1[2] ; dout1[2]~reg0 ; clk ;
; N/A ; None ; 4.088 ns ; din1[1] ; dout1[1]~reg0 ; clk ;
; N/A ; None ; 4.060 ns ; din1[0] ; dout1[0]~reg0 ; clk ;
; N/A ; None ; 4.028 ns ; read_comp ; result~reg0 ; clk ;
; N/A ; None ; 3.980 ns ; din1[3] ; dout1[3]~reg0 ; clk ;
; N/A ; None ; 3.698 ns ; din10[2] ; dout10[2]~reg0 ; clk ;
; N/A ; None ; 3.610 ns ; din10[1] ; dout10[1]~reg0 ; clk ;
; N/A ; None ; 3.598 ns ; din10[3] ; dout10[3]~reg0 ; clk ;
; N/A ; None ; 3.574 ns ; din10[0] ; dout10[0]~reg0 ; clk ;
+-------+--------------+------------+-----------+----------------+----------+
+-----------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A ; None ; 6.859 ns ; dout10[0]~reg0 ; dout10[0] ; clk ;
; N/A ; None ; 6.841 ns ; dout1[0]~reg0 ; dout1[0] ; clk ;
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