reg_comp.map.rpt

4X4 KEYPAD 的密码比较模块

+-----------+
reg_comp


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |reg_comp                  ; 14 (14)     ; 9            ; 0           ; 21   ; 0            ; 5 (5)        ; 8 (8)             ; 1 (1)            ; 0 (0)           ; |reg_comp           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------+-------------------------+
; File Name    ; Used in Netlist         ;
+--------------+-------------------------+
; reg_comp.vhd ; yes                     ;
+--------------+-------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 14        ;
; Total combinational functions   ; 6         ;
; Total 4-input functions         ; 5         ;
; Total 3-input functions         ; 0         ;
; Total 2-input functions         ; 1         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 9         ;
; I/O pins                        ; 21        ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 9         ;
; Total fan-out                   ; 66        ;
; Average fan-out                 ; 1.89      ;
+---------------------------------+-----------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 14    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 6     ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 9     ;
; Number of cells with combinational logic only          ; 5     ;
; Number of cells with registers only                    ; 8     ;
; Number of cells with combinational logic and registers ; 1     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Oct 31 05:27:31 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off reg_comp -c reg_comp
Info: Found 2 design units, including 1 entities, in source file reg_comp.vhd
    Info: Found design unit 1: reg_comp-reg_comp_architecture
    Info: Found entity 1: reg_comp
Info: Duplicate registers merged to single register
    Info: Duplicate register temp_din10[3] merged to single register dout10[3]~reg0
    Info: Duplicate register temp_din10[2] merged to single register dout10[2]~reg0
    Info: Duplicate register temp_din10[1] merged to single register dout10[1]~reg0
    Info: Duplicate register temp_din10[0] merged to single register dout10[0]~reg0
    Info: Duplicate register temp_din1[3] merged to single register dout1[3]~reg0
    Info: Duplicate register temp_din1[2] merged to single register dout1[2]~reg0
    Info: Duplicate register temp_din1[1] merged to single register dout1[1]~reg0
    Info: Duplicate register temp_din1[0] merged to single register dout1[0]~reg0
Warning: Feature Netlist Optimizations is not available with your current license
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 9 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 31 05:27:33 2004
    Info: Elapsed time: 00:00:01