debounce.map.rpt

4X4keypad的防抖动模块

+--------------------------------------------------------------------------------------------+-------------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
debounce


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |debounce                  ; 2 (2)       ; 2            ; 0           ; 6    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; 0 (0)           ; |debounce           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------+-------------------------+
; File Name    ; Used in Netlist         ;
+--------------+-------------------------+
; debounce.vhd ; yes                     ;
+--------------+-------------------------+


+----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary  ;
+---------------------------------+------------+
; Resource                        ; Usage      ;
+---------------------------------+------------+
; Logic cells                     ; 2          ;
; Total combinational functions   ; 2          ;
; Total 4-input functions         ; 1          ;
; Total 3-input functions         ; 1          ;
; Total 2-input functions         ; 0          ;
; Total 1-input functions         ; 0          ;
; Total 0-input functions         ; 0          ;
; Combinational cells for routing ; 0          ;
; Total registers                 ; 2          ;
; I/O pins                        ; 6          ;
; Maximum fan-out node            ; p_state[0] ;
; Maximum fan-out                 ; 3          ;
; Total fan-out                   ; 13         ;
; Average fan-out                 ; 1.63       ;
+---------------------------------+------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 2     ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 2     ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 2     ;
; Number of cells with combinational logic only          ; 0     ;
; Number of cells with registers only                    ; 0     ;
; Number of cells with combinational logic and registers ; 2     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 2     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Nov 01 16:48:19 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off debounce -c debounce
Info: Found 2 design units, including 1 entities, in source file debounce.vhd
    Info: Found design unit 1: debounce-debounce_architecture
    Info: Found entity 1: debounce
Warning: Feature Netlist Optimizations is not available with your current license
Info: Implemented 8 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 2 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Nov 01 16:48:20 2004
    Info: Elapsed time: 00:00:01