debounce.tan.qmsg

4X4keypad的防抖动模块

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk START p_state\[0\] 6.229 ns register " "Info: Minimum tco from clock clk to destination pin START through register p_state\[0\] is 6.229 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.736 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[0\] 2 REG LC3_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.059 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[0\] 1 REG LC3_1_Q1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(2.566 ns) 3.059 ns START 2 PIN PIN_M3 0 " "Info: 2: + IC(0.284 ns) + CELL(2.566 ns) = 3.059 ns; Loc. = PIN_M3; Fanout = 0; PIN Node = 'START'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.850 ns" { p_state[0] START } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.775 ns 90.72 % " "Info: Total cell delay = 2.775 ns ( 90.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.284 ns 9.28 % " "Info: Total interconnect delay = 0.284 ns ( 9.28 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "3.059 ns" { p_state[0] START } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "3.059 ns" { p_state[0] START } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 01 16:48:37 2004 " "Info: Processing ended: Mon Nov 01 16:48:37 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}