📄 debounce.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } { "c:/altera/quartus41sp2/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register p_state\[1\] p_state\[1\] 233.64 MHz Internal " "Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register p_state\[1\] and destination register p_state\[1\]" { { "Info" "ITDB_CLOCK_RATE" "clock 4.28 ns " "Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.301 ns + Longest register register " "Info: + Longest register to register delay is 1.301 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[1\] 1 REG LC5_1_Q1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.789 ns) 1.301 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(0.303 ns) + CELL(0.789 ns) = 1.301 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.092 ns" { p_state[1] p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.998 ns 76.71 % " "Info: Total cell delay = 0.998 ns ( 76.71 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.303 ns 23.29 % " "Info: Total interconnect delay = 0.303 ns ( 23.29 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.301 ns" { p_state[1] p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.736 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.736 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.301 ns" { p_state[1] p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "p_state\[1\] done clk 3.002 ns register " "Info: tsu for register p_state\[1\] (data pin = done, clock pin = clk) is 3.002 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.574 ns + Longest pin register " "Info: + Longest pin to register delay is 5.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns done 1 PIN PIN_U5 2 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_U5; Fanout = 2; PIN Node = 'done'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { done } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.929 ns) + CELL(0.899 ns) 5.574 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(2.929 ns) + CELL(0.899 ns) = 5.574 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "3.828 ns" { done p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.645 ns 47.45 % " "Info: Total cell delay = 2.645 ns ( 47.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.929 ns 52.55 % " "Info: Total interconnect delay = 2.929 ns ( 52.55 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.574 ns" { done p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.736 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.574 ns" { done p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk SWdown p_state\[1\] 8.245 ns register " "Info: tco from clock clk to destination pin SWdown through register p_state\[1\] is 8.245 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.736 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[1\] 2 REG LC5_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.075 ns + Longest register pin " "Info: + Longest register to pin delay is 5.075 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[1\] 1 REG LC5_1_Q1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.566 ns) 5.075 ns SWdown 2 PIN PIN_J5 0 " "Info: 2: + IC(2.300 ns) + CELL(2.566 ns) = 5.075 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'SWdown'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "4.866 ns" { p_state[1] SWdown } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.775 ns 54.68 % " "Info: Total cell delay = 2.775 ns ( 54.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 45.32 % " "Info: Total interconnect delay = 2.300 ns ( 45.32 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.075 ns" { p_state[1] SWdown } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.075 ns" { p_state[1] SWdown } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "p_state\[0\] SW clk -2.457 ns register " "Info: th for register p_state\[0\] (data pin = SW, clock pin = clk) is -2.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.736 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.000 ns) 2.736 ns p_state\[0\] 2 REG LC3_1_Q1 3 " "Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "1.363 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.18 % " "Info: Total cell delay = 1.373 ns ( 50.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.363 ns 49.82 % " "Info: Total interconnect delay = 1.363 ns ( 49.82 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.349 ns + " "Info: + Micro hold delay of destination is 0.349 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.542 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns SW 1 PIN PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_N1; Fanout = 1; PIN Node = 'SW'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "" { SW } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.927 ns) + CELL(0.869 ns) 5.542 ns p_state\[0\] 2 REG LC3_1_Q1 3 " "Info: 2: + IC(2.927 ns) + CELL(0.869 ns) = 5.542 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "3.796 ns" { SW p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/debounce.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.615 ns 47.19 % " "Info: Total cell delay = 2.615 ns ( 47.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.927 ns 52.81 % " "Info: Total interconnect delay = 2.927 ns ( 52.81 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.542 ns" { SW p_state[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "2.736 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce_cmp.qrpt" Compiler "debounce" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/debounce/db/debounce.quartus_db" { Floorplan "" "" "5.542 ns" { SW p_state[0] } "NODE_NAME" } } } } 0}
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