debounce.tan.rpt

4X4keypad的防抖动模块

; tco                                                                  ;
+-------+--------------+------------+------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To     ; From Clock ;
+-------+--------------+------------+------------+--------+------------+
; N/A   ; None         ; 8.245 ns   ; p_state[1] ; SWdown ; clk        ;
; N/A   ; None         ; 6.229 ns   ; p_state[0] ; START  ; clk        ;
+-------+--------------+------------+------------+--------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To         ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A           ; None        ; -2.457 ns ; SW   ; p_state[0] ; clk      ;
; N/A           ; None        ; -2.483 ns ; done ; p_state[0] ; clk      ;
; N/A           ; None        ; -2.489 ns ; done ; p_state[1] ; clk      ;
+---------------+-------------+-----------+------+------------+----------+


+--------------------------------------------------------------------------------------+
; Minimum tco                                                                          ;
+---------------+------------------+----------------+------------+--------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From       ; To     ; From Clock ;
+---------------+------------------+----------------+------------+--------+------------+
; N/A           ; None             ; 6.229 ns       ; p_state[0] ; START  ; clk        ;
; N/A           ; None             ; 8.245 ns       ; p_state[1] ; SWdown ; clk        ;
+---------------+------------------+----------------+------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Nov 01 16:48:35 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off debounce -c debounce
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register p_state[1] and destination register p_state[1]
    Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.301 ns
            Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
            Info: 2: + IC(0.303 ns) + CELL(0.789 ns) = 1.301 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
            Info: Total cell delay = 0.998 ns ( 76.71 % )
            Info: Total interconnect delay = 0.303 ns ( 23.29 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.736 ns
                Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
                Info: Total cell delay = 1.373 ns ( 50.18 % )
                Info: Total interconnect delay = 1.363 ns ( 49.82 % )
            Info: - Longest clock path from clock clk to source register is 2.736 ns
                Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
                Info: Total cell delay = 1.373 ns ( 50.18 % )
                Info: Total interconnect delay = 1.363 ns ( 49.82 % )
        Info: + Micro clock to output delay of source is 0.434 ns
        Info: + Micro setup delay of destination is 0.164 ns
Info: tsu for register p_state[1] (data pin = done, clock pin = clk) is 3.002 ns
    Info: + Longest pin to register delay is 5.574 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_U5; Fanout = 2; PIN Node = 'done'
        Info: 2: + IC(2.929 ns) + CELL(0.899 ns) = 5.574 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
        Info: Total cell delay = 2.645 ns ( 47.45 % )
        Info: Total interconnect delay = 2.929 ns ( 52.55 % )
    Info: + Micro setup delay of destination is 0.164 ns
    Info: - Shortest clock path from clock clk to destination register is 2.736 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
        Info: Total cell delay = 1.373 ns ( 50.18 % )
        Info: Total interconnect delay = 1.363 ns ( 49.82 % )
Info: tco from clock clk to destination pin SWdown through register p_state[1] is 8.245 ns
    Info: + Longest clock path from clock clk to source register is 2.736 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
        Info: Total cell delay = 1.373 ns ( 50.18 % )
        Info: Total interconnect delay = 1.363 ns ( 49.82 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Longest register to pin delay is 5.075 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_1_Q1; Fanout = 3; REG Node = 'p_state[1]'
        Info: 2: + IC(2.300 ns) + CELL(2.566 ns) = 5.075 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'SWdown'
        Info: Total cell delay = 2.775 ns ( 54.68 % )
        Info: Total interconnect delay = 2.300 ns ( 45.32 % )
Info: th for register p_state[0] (data pin = SW, clock pin = clk) is -2.457 ns
    Info: + Longest clock path from clock clk to destination register is 2.736 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state[0]'
        Info: Total cell delay = 1.373 ns ( 50.18 % )
        Info: Total interconnect delay = 1.363 ns ( 49.82 % )
    Info: + Micro hold delay of destination is 0.349 ns
    Info: - Shortest pin to register delay is 5.542 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_N1; Fanout = 1; PIN Node = 'SW'
        Info: 2: + IC(2.927 ns) + CELL(0.869 ns) = 5.542 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state[0]'
        Info: Total cell delay = 2.615 ns ( 47.19 % )
        Info: Total interconnect delay = 2.927 ns ( 52.81 % )
Info: Minimum tco from clock clk to destination pin START through register p_state[0] is 6.229 ns
    Info: + Shortest clock path from clock clk to source register is 2.736 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.363 ns) + CELL(0.000 ns) = 2.736 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state[0]'
        Info: Total cell delay = 1.373 ns ( 50.18 % )
        Info: Total interconnect delay = 1.363 ns ( 49.82 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Shortest register to pin delay is 3.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC3_1_Q1; Fanout = 3; REG Node = 'p_state[0]'
        Info: 2: + IC(0.284 ns) + CELL(2.566 ns) = 3.059 ns; Loc. = PIN_M3; Fanout = 0; PIN Node = 'START'
        Info: Total cell delay = 2.775 ns ( 90.72 % )
        Info: Total interconnect delay = 0.284 ns ( 9.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Nov 01 16:48:37 2004
    Info: Elapsed time: 00:00:02