control.tan.rpt

4X4电子密码锁的中央控制系统。控制6位输入。

; tco                                                              ;
+-------+--------------+------------+------------+----+------------+
; Slack ; Required tco ; Actual tco ; From       ; To ; From Clock ;
+-------+--------------+------------+------------+----+------------+
; N/A   ; None         ; 11.537 ns  ; p_state[2] ; RE ; clk        ;
; N/A   ; None         ; 11.406 ns  ; p_state[0] ; RE ; clk        ;
; N/A   ; None         ; 11.062 ns  ; p_state[1] ; RE ; clk        ;
; N/A   ; None         ; 10.895 ns  ; p_state[3] ; RE ; clk        ;
+-------+--------------+------------+------------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+------------+-----------+------------+----------+
; Minimum Slack ; Required th ; Actual th  ; From      ; To         ; To Clock ;
+---------------+-------------+------------+-----------+------------+----------+
; N/A           ; None        ; -3.178 ns  ; num_re    ; p_state[0] ; clk      ;
; N/A           ; None        ; -3.859 ns  ; num_re    ; p_state[1] ; clk      ;
; N/A           ; None        ; -3.861 ns  ; num_re    ; p_state[3] ; clk      ;
; N/A           ; None        ; -7.197 ns  ; result[1] ; p_state[2] ; clk      ;
; N/A           ; None        ; -8.477 ns  ; result[1] ; p_state[3] ; clk      ;
; N/A           ; None        ; -8.829 ns  ; result[2] ; p_state[2] ; clk      ;
; N/A           ; None        ; -9.781 ns  ; result[0] ; p_state[2] ; clk      ;
; N/A           ; None        ; -9.901 ns  ; result[4] ; p_state[2] ; clk      ;
; N/A           ; None        ; -10.056 ns ; result[3] ; p_state[2] ; clk      ;
; N/A           ; None        ; -10.109 ns ; result[2] ; p_state[3] ; clk      ;
; N/A           ; None        ; -10.690 ns ; result[5] ; p_state[2] ; clk      ;
; N/A           ; None        ; -11.061 ns ; result[0] ; p_state[3] ; clk      ;
; N/A           ; None        ; -11.181 ns ; result[4] ; p_state[3] ; clk      ;
; N/A           ; None        ; -11.336 ns ; result[3] ; p_state[3] ; clk      ;
; N/A           ; None        ; -11.970 ns ; result[5] ; p_state[3] ; clk      ;
+---------------+-------------+------------+-----------+------------+----------+


+----------------------------------------------------------------------------------+
; Minimum tco                                                                      ;
+---------------+------------------+----------------+------------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From       ; To ; From Clock ;
+---------------+------------------+----------------+------------+----+------------+
; N/A           ; None             ; 9.417 ns       ; p_state[3] ; RE ; clk        ;
; N/A           ; None             ; 9.928 ns       ; p_state[0] ; RE ; clk        ;
; N/A           ; None             ; 10.040 ns      ; p_state[2] ; RE ; clk        ;
; N/A           ; None             ; 10.095 ns      ; p_state[1] ; RE ; clk        ;
+---------------+------------------+----------------+------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Thu Nov 11 05:12:21 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off control -c control
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 212.54 MHz between source register p_state[2] and destination register p_state[0] (period= 4.705 ns)
    Info: + Longest register to register delay is 4.107 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state[2]'
        Info: 2: + IC(0.375 ns) + CELL(1.139 ns) = 1.723 ns; Loc. = LC2_4_U2; Fanout = 2; COMB Node = 'n_state~378'
        Info: 3: + IC(0.316 ns) + CELL(1.034 ns) = 3.073 ns; Loc. = LC8_4_U2; Fanout = 2; COMB Node = 'n_state[0]~379'
        Info: 4: + IC(0.375 ns) + CELL(0.659 ns) = 4.107 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state[0]'
        Info: Total cell delay = 3.041 ns ( 74.04 % )
        Info: Total interconnect delay = 1.066 ns ( 25.96 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 2.740 ns
            Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state[0]'
            Info: Total cell delay = 1.373 ns ( 50.11 % )
            Info: Total interconnect delay = 1.367 ns ( 49.89 % )
        Info: - Longest clock path from clock clk to source register is 2.740 ns
            Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state[2]'
            Info: Total cell delay = 1.373 ns ( 50.11 % )
            Info: Total interconnect delay = 1.367 ns ( 49.89 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Micro setup delay of destination is 0.164 ns
Info: tsu for register p_state[3] (data pin = result[5], clock pin = clk) is 12.483 ns
    Info: + Longest pin to register delay is 15.059 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_K7; Fanout = 1; PIN Node = 'result[5]'
        Info: 2: + IC(2.927 ns) + CELL(1.139 ns) = 5.812 ns; Loc. = LC3_1_J1; Fanout = 1; COMB Node = 'reduce_nor~96'
        Info: 3: + IC(3.163 ns) + CELL(0.464 ns) = 9.439 ns; Loc. = LC3_5_J2; Fanout = 2; COMB Node = 'reduce_nor~3'
        Info: 4: + IC(3.481 ns) + CELL(1.034 ns) = 13.954 ns; Loc. = LC10_4_U2; Fanout = 1; COMB Node = 'n_state[3]~380'
        Info: 5: + IC(0.316 ns) + CELL(0.789 ns) = 15.059 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state[3]'
        Info: Total cell delay = 5.172 ns ( 34.34 % )
        Info: Total interconnect delay = 9.887 ns ( 65.66 % )
    Info: + Micro setup delay of destination is 0.164 ns
    Info: - Shortest clock path from clock clk to destination register is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state[3]'
        Info: Total cell delay = 1.373 ns ( 50.11 % )
        Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: tco from clock clk to destination pin RE through register p_state[2] is 11.537 ns
    Info: + Longest clock path from clock clk to source register is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state[2]'
        Info: Total cell delay = 1.373 ns ( 50.11 % )
        Info: Total interconnect delay = 1.367 ns ( 49.89 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Longest register to pin delay is 8.363 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state[2]'
        Info: 2: + IC(0.375 ns) + CELL(1.139 ns) = 1.723 ns; Loc. = LC2_4_U2; Fanout = 2; COMB Node = 'n_state~378'
        Info: 3: + IC(0.316 ns) + CELL(1.034 ns) = 3.073 ns; Loc. = LC8_4_U2; Fanout = 2; COMB Node = 'n_state[0]~379'
        Info: 4: + IC(0.375 ns) + CELL(1.154 ns) = 4.602 ns; Loc. = LC3_5_U2; Fanout = 2; COMB Node = 'RE$latch~130'
        Info: 5: + IC(1.195 ns) + CELL(2.566 ns) = 8.363 ns; Loc. = PIN_T17; Fanout = 0; PIN Node = 'RE'
        Info: Total cell delay = 6.102 ns ( 72.96 % )
        Info: Total interconnect delay = 2.261 ns ( 27.04 % )
Info: th for register p_state[0] (data pin = num_re, clock pin = clk) is -3.178 ns
    Info: + Longest clock path from clock clk to destination register is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state[0]'
        Info: Total cell delay = 1.373 ns ( 50.11 % )
        Info: Total interconnect delay = 1.367 ns ( 49.89 % )
    Info: + Micro hold delay of destination is 0.349 ns
    Info: - Shortest pin to register delay is 6.267 ns
        Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_P19; Fanout = 3; PIN Node = 'num_re'
        Info: 2: + IC(4.327 ns) + CELL(0.194 ns) = 6.267 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state[0]'
        Info: Total cell delay = 1.940 ns ( 30.96 % )
        Info: Total interconnect delay = 4.327 ns ( 69.04 % )
Info: Minimum tco from clock clk to destination pin RE through register p_state[3] is 9.417 ns
    Info: + Shortest clock path from clock clk to source register is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state[3]'
        Info: Total cell delay = 1.373 ns ( 50.11 % )
        Info: Total interconnect delay = 1.367 ns ( 49.89 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Shortest register to pin delay is 6.243 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state[3]'
        Info: 2: + IC(0.408 ns) + CELL(0.464 ns) = 1.081 ns; Loc. = LC3_4_U2; Fanout = 2; COMB Node = 'reduce_nor~2'
        Info: 3: + IC(0.367 ns) + CELL(1.034 ns) = 2.482 ns; Loc. = LC3_5_U2; Fanout = 2; COMB Node = 'RE$latch~130'
        Info: 4: + IC(1.195 ns) + CELL(2.566 ns) = 6.243 ns; Loc. = PIN_T17; Fanout = 0; PIN Node = 'RE'
        Info: Total cell delay = 4.273 ns ( 68.44 % )
        Info: Total interconnect delay = 1.970 ns ( 31.56 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 11 05:12:24 2004
    Info: Elapsed time: 00:00:02