control.tan.qmsg

4X4电子密码锁的中央控制系统。控制6位输入。

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk RE p_state\[3\] 9.417 ns register " "Info: Minimum tco from clock clk to destination pin RE through register p_state\[3\] is 9.417 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[3\] 2 REG LC5_4_U2 5 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state\[3\]'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" {  } {  } 0}  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.243 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[3\] 1 REG LC5_4_U2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state\[3\]'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.464 ns) 1.081 ns reduce_nor~2 2 COMB LC3_4_U2 2 " "Info: 2: + IC(0.408 ns) + CELL(0.464 ns) = 1.081 ns; Loc. = LC3_4_U2; Fanout = 2; COMB Node = 'reduce_nor~2'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "0.872 ns" { p_state[3] reduce_nor~2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(1.034 ns) 2.482 ns RE\$latch~130 3 COMB LC3_5_U2 2 " "Info: 3: + IC(0.367 ns) + CELL(1.034 ns) = 2.482 ns; Loc. = LC3_5_U2; Fanout = 2; COMB Node = 'RE\$latch~130'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.401 ns" { reduce_nor~2 RE$latch~130 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(2.566 ns) 6.243 ns RE 4 PIN PIN_T17 0 " "Info: 4: + IC(1.195 ns) + CELL(2.566 ns) = 6.243 ns; Loc. = PIN_T17; Fanout = 0; PIN Node = 'RE'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "3.761 ns" { RE$latch~130 RE } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.273 ns 68.44 % " "Info: Total cell delay = 4.273 ns ( 68.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.970 ns 31.56 % " "Info: Total interconnect delay = 1.970 ns ( 31.56 % )" {  } {  } 0}  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "6.243 ns" { p_state[3] reduce_nor~2 RE$latch~130 RE } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "6.243 ns" { p_state[3] reduce_nor~2 RE$latch~130 RE } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 05:12:24 2004 " "Info: Processing ended: Thu Nov 11 05:12:24 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}