📄 control.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } { "c:/altera/quartus41sp2/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register p_state\[2\] register p_state\[0\] 212.54 MHz 4.705 ns Internal " "Info: Clock clk has Internal fmax of 212.54 MHz between source register p_state\[2\] and destination register p_state\[0\] (period= 4.705 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.107 ns + Longest register register " "Info: + Longest register to register delay is 4.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[2\] 1 REG LC7_4_U2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(1.139 ns) 1.723 ns n_state~378 2 COMB LC2_4_U2 2 " "Info: 2: + IC(0.375 ns) + CELL(1.139 ns) = 1.723 ns; Loc. = LC2_4_U2; Fanout = 2; COMB Node = 'n_state~378'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.514 ns" { p_state[2] n_state~378 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(1.034 ns) 3.073 ns n_state\[0\]~379 3 COMB LC8_4_U2 2 " "Info: 3: + IC(0.316 ns) + CELL(1.034 ns) = 3.073 ns; Loc. = LC8_4_U2; Fanout = 2; COMB Node = 'n_state\[0\]~379'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.350 ns" { n_state~378 n_state[0]~379 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.659 ns) 4.107 ns p_state\[0\] 4 REG LC1_4_U2 5 " "Info: 4: + IC(0.375 ns) + CELL(0.659 ns) = 4.107 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.034 ns" { n_state[0]~379 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.041 ns 74.04 % " "Info: Total cell delay = 3.041 ns ( 74.04 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns 25.96 % " "Info: Total interconnect delay = 1.066 ns ( 25.96 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.107 ns" { p_state[2] n_state~378 n_state[0]~379 p_state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[0\] 2 REG LC1_4_U2 5 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[2\] 2 REG LC7_4_U2 6 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.107 ns" { p_state[2] n_state~378 n_state[0]~379 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "p_state\[3\] result\[5\] clk 12.483 ns register " "Info: tsu for register p_state\[3\] (data pin = result\[5\], clock pin = clk) is 12.483 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.059 ns + Longest pin register " "Info: + Longest pin to register delay is 15.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns result\[5\] 1 PIN PIN_K7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_K7; Fanout = 1; PIN Node = 'result\[5\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { result[5] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.927 ns) + CELL(1.139 ns) 5.812 ns reduce_nor~96 2 COMB LC3_1_J1 1 " "Info: 2: + IC(2.927 ns) + CELL(1.139 ns) = 5.812 ns; Loc. = LC3_1_J1; Fanout = 1; COMB Node = 'reduce_nor~96'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.066 ns" { result[5] reduce_nor~96 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.163 ns) + CELL(0.464 ns) 9.439 ns reduce_nor~3 3 COMB LC3_5_J2 2 " "Info: 3: + IC(3.163 ns) + CELL(0.464 ns) = 9.439 ns; Loc. = LC3_5_J2; Fanout = 2; COMB Node = 'reduce_nor~3'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "3.627 ns" { reduce_nor~96 reduce_nor~3 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.481 ns) + CELL(1.034 ns) 13.954 ns n_state\[3\]~380 4 COMB LC10_4_U2 1 " "Info: 4: + IC(3.481 ns) + CELL(1.034 ns) = 13.954 ns; Loc. = LC10_4_U2; Fanout = 1; COMB Node = 'n_state\[3\]~380'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.515 ns" { reduce_nor~3 n_state[3]~380 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.789 ns) 15.059 ns p_state\[3\] 5 REG LC5_4_U2 5 " "Info: 5: + IC(0.316 ns) + CELL(0.789 ns) = 15.059 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state\[3\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.105 ns" { n_state[3]~380 p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.172 ns 34.34 % " "Info: Total cell delay = 5.172 ns ( 34.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.887 ns 65.66 % " "Info: Total interconnect delay = 9.887 ns ( 65.66 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "15.059 ns" { result[5] reduce_nor~96 reduce_nor~3 n_state[3]~380 p_state[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[3\] 2 REG LC5_4_U2 5 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC5_4_U2; Fanout = 5; REG Node = 'p_state\[3\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[3] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "15.059 ns" { result[5] reduce_nor~96 reduce_nor~3 n_state[3]~380 p_state[3] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk RE p_state\[2\] 11.537 ns register " "Info: tco from clock clk to destination pin RE through register p_state\[2\] is 11.537 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[2\] 2 REG LC7_4_U2 6 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.363 ns + Longest register pin " "Info: + Longest register to pin delay is 8.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[2\] 1 REG LC7_4_U2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC7_4_U2; Fanout = 6; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(1.139 ns) 1.723 ns n_state~378 2 COMB LC2_4_U2 2 " "Info: 2: + IC(0.375 ns) + CELL(1.139 ns) = 1.723 ns; Loc. = LC2_4_U2; Fanout = 2; COMB Node = 'n_state~378'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.514 ns" { p_state[2] n_state~378 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(1.034 ns) 3.073 ns n_state\[0\]~379 3 COMB LC8_4_U2 2 " "Info: 3: + IC(0.316 ns) + CELL(1.034 ns) = 3.073 ns; Loc. = LC8_4_U2; Fanout = 2; COMB Node = 'n_state\[0\]~379'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.350 ns" { n_state~378 n_state[0]~379 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(1.154 ns) 4.602 ns RE\$latch~130 4 COMB LC3_5_U2 2 " "Info: 4: + IC(0.375 ns) + CELL(1.154 ns) = 4.602 ns; Loc. = LC3_5_U2; Fanout = 2; COMB Node = 'RE\$latch~130'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.529 ns" { n_state[0]~379 RE$latch~130 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 61 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(2.566 ns) 8.363 ns RE 5 PIN PIN_T17 0 " "Info: 5: + IC(1.195 ns) + CELL(2.566 ns) = 8.363 ns; Loc. = PIN_T17; Fanout = 0; PIN Node = 'RE'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "3.761 ns" { RE$latch~130 RE } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.102 ns 72.96 % " "Info: Total cell delay = 6.102 ns ( 72.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.261 ns 27.04 % " "Info: Total interconnect delay = 2.261 ns ( 27.04 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "8.363 ns" { p_state[2] n_state~378 n_state[0]~379 RE$latch~130 RE } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "8.363 ns" { p_state[2] n_state~378 n_state[0]~379 RE$latch~130 RE } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "p_state\[0\] num_re clk -3.178 ns register " "Info: th for register p_state\[0\] (data pin = num_re, clock pin = clk) is -3.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 4; CLK Node = 'clk'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[0\] 2 REG LC1_4_U2 5 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.349 ns + " "Info: + Micro hold delay of destination is 0.349 ns" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.267 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns num_re 1 PIN PIN_P19 3 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_P19; Fanout = 3; PIN Node = 'num_re'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { num_re } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.327 ns) + CELL(0.194 ns) 6.267 ns p_state\[0\] 2 REG LC1_4_U2 5 " "Info: 2: + IC(4.327 ns) + CELL(0.194 ns) = 6.267 ns; Loc. = LC1_4_U2; Fanout = 5; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.521 ns" { num_re p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.940 ns 30.96 % " "Info: Total cell delay = 1.940 ns ( 30.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.327 ns 69.04 % " "Info: Total interconnect delay = 4.327 ns ( 69.04 % )" { } { } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "6.267 ns" { num_re p_state[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "6.267 ns" { num_re p_state[0] } "NODE_NAME" } } } } 0}
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