control.fit.qmsg

4X4电子密码锁的中央控制系统。控制6位输入。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 05:12:03 2004 " "Info: Processing started: Thu Nov 11 05:12:03 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off control -c control " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off control -c control" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "control EP20K200EFC484-2X " "Info: Selected device EP20K200EFC484-2X for design control" {  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "SignalProbe " "Warning: Feature SignalProbe is not available with your current license" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell clk to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "state~0 automatically " "Info: Promoted cell state~0 to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Thu Nov 11 2004 05:12:08 " "Info: Started fitting attempt 1 on Thu Nov 11 2004 at 05:12:08" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "1 " "Info: Maximum row FastTrack interconnect = 1%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.028 ns register register " "Info: Estimated most critical path is register to register delay of 4.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[1\] 1 REG LAB_4_U2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LAB_4_U2; Fanout = 6; REG Node = 'p_state\[1\]'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "" { p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(1.154 ns) 1.647 ns reduce_nor~95 2 COMB LAB_4_U2 2 " "Info: 2: + IC(0.284 ns) + CELL(1.154 ns) = 1.647 ns; Loc. = LAB_4_U2; Fanout = 2; COMB Node = 'reduce_nor~95'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.438 ns" { p_state[1] reduce_nor~95 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(1.154 ns) 3.085 ns n_state\[0\]~379 3 COMB LAB_4_U2 2 " "Info: 3: + IC(0.284 ns) + CELL(1.154 ns) = 3.085 ns; Loc. = LAB_4_U2; Fanout = 2; COMB Node = 'n_state\[0\]~379'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "1.438 ns" { reduce_nor~95 n_state[0]~379 } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.659 ns) 4.028 ns p_state\[0\] 4 REG LAB_4_U2 5 " "Info: 4: + IC(0.284 ns) + CELL(0.659 ns) = 4.028 ns; Loc. = LAB_4_U2; Fanout = 5; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "0.943 ns" { n_state[0]~379 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" "" "" { Text "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.176 ns 78.85 % " "Info: Total cell delay = 3.176 ns ( 78.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.852 ns 21.15 % " "Info: Total interconnect delay = 0.852 ns ( 21.15 % )" {  } {  } 0}  } { { "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" "" "" { Report "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control_cmp.qrpt" Compiler "control" "UNKNOWN" "V1" "D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/db/control.quartus_db" { Floorplan "" "" "4.028 ns" { p_state[1] reduce_nor~95 n_state[0]~379 p_state[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "5 " "Info: Fitter routing operations ending: elapsed time = 5 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 05:12:14 2004 " "Info: Processing ended: Thu Nov 11 05:12:14 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}