control.vhd

4X4电子密码锁的中央控制系统。控制6位输入。

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sun Oct 24 16:27:39 2004

-- control the buffer_display and reg_comp to read a number
-- or read again when it is the same as before

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY control IS
	PORT
	(
	     signal num_re,stop,reset,clk: in std_logic;
	     signal result: in std_logic_vector (5 downto 0);
	     signal RE: out std_logic
	);
END control;

ARCHITECTURE control_architecture OF control IS
    constant s0 :std_logic_vector(3 downto 0):="0001"; 
	constant s1 :std_logic_vector(3 downto 0):="0010";
	constant s2 :std_logic_vector(3 downto 0):="0100";
	constant s3 :std_logic_vector(3 downto 0):="1000";
	signal n_state: std_logic_vector (3 downto 0);
	signal p_state: std_logic_vector (3 downto 0);
BEGIN
   state:process(reset,clk,stop)
   begin
    if (reset='0' or stop='1') then
           p_state<=s0;
    elsif (clk'event and clk='1') then
           p_state<=n_state;
    end if;
    end process state;

    comb:process(p_state,num_re,result,clk)
    begin
          n_state<=p_state;
       if (p_state=s0) then -- num_re is low when SW5 is push down
           RE<='1';
           if num_re='1' then
              n_state<=s0;
           elsif num_re='0' then
              n_state<=s1;
           end if;
       end if;

       if (p_state=s1) then 
             RE<='0';
             n_state<=s2;
       end if;

       if (p_state=s2) then
          RE<='0';
          if (result="000000") then 
                 n_state<=s3;
          else
                n_state<=s2; -- if the number read is the same
                             -- as before, read again
          end if;
       end if;

       if (p_state=s3) then
             RE<='1';
          if num_re='0' then
              n_state<=s3;
          elsif num_re='1' then
              n_state<=s0;
          end if;
       end if;
   end process comb;	
END control_architecture;