control.map.rpt

4X4电子密码锁的中央控制系统。控制6位输入。

+-----------+
; Hierarchy ;
+-----------+
control


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |control                   ; 14 (14)     ; 4            ; 0           ; 11   ; 0            ; 10 (10)      ; 1 (1)             ; 3 (3)            ; 0 (0)           ; |control            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------+--------------------------+
; File Name   ; Used in Netlist          ;
+-------------+--------------------------+
; control.vhd ; yes                      ;
+-------------+--------------------------+


+----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary  ;
+---------------------------------+------------+
; Resource                        ; Usage      ;
+---------------------------------+------------+
; Logic cells                     ; 14         ;
; Total combinational functions   ; 13         ;
; Total 4-input functions         ; 9          ;
; Total 3-input functions         ; 3          ;
; Total 2-input functions         ; 1          ;
; Total 1-input functions         ; 0          ;
; Total 0-input functions         ; 0          ;
; Combinational cells for routing ; 0          ;
; Total registers                 ; 4          ;
; I/O pins                        ; 11         ;
; Maximum fan-out node            ; p_state[1] ;
; Maximum fan-out                 ; 6          ;
; Total fan-out                   ; 58         ;
; Average fan-out                 ; 2.32       ;
+---------------------------------+------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 1     ;
; Number of synthesis-generated cells                    ; 13    ;
; Number of WYSIWYG LUTs                                 ; 1     ;
; Number of synthesis-generated LUTs                     ; 12    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 4     ;
; Number of cells with combinational logic only          ; 10    ;
; Number of cells with registers only                    ; 1     ;
; Number of cells with combinational logic and registers ; 3     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Thu Nov 11 05:12:01 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off control -c control
Info: Found 2 design units, including 1 entities, in source file control.vhd
    Info: Found design unit 1: control-control_architecture
    Info: Found entity 1: control
Warning: VHDL Process Statement warning at control.vhd(61): signal or variable re may not be assigned a new value in every possible path through the Process Statement. Signal or variable re holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 1 buffer(s)
    Info: Ignored 1 SOFT buffer(s)
Warning: Feature Netlist Optimizations is not available with your current license
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 25 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 1 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Nov 11 05:12:02 2004
    Info: Elapsed time: 00:00:01