control.map.rpt

4X4电子密码锁的中央控制系统。控制6位输入。

Analysis & Synthesis report for control
Thu Nov 11 05:12:02 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. Analysis & Synthesis Resource Utilization by Entity
  6. Analysis & Synthesis Equations
  7. Analysis & Synthesis Source Files Read
  8. Analysis & Synthesis Resource Usage Summary
  9. WYSIWYG Cells
 10. General Register Statistics
 11. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Nov 11 05:12:02 2004        ;
; Quartus II Version          ; 4.1 Build 208 09/10/2004 SP 2 SJ Web Edition ;
; Revision Name               ; control                                      ;
; Top-level Entity Name       ; control                                      ;
; Family                      ; APEX20KE                                     ;
; Total logic elements        ; 14                                           ;
; Total pins                  ; 11                                           ;
; Total memory bits           ; 0                                            ;
; Total PLLs                  ; 0                                            ;
+-----------------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                  ;
+--------------------------------------------------------------------------------------------+-------------------+---------------+
; Option                                                                                     ; Setting           ; Default Value ;
+--------------------------------------------------------------------------------------------+-------------------+---------------+
; Device                                                                                     ; EP20K200EFC484-2X ;               ;
; Family name                                                                                ; APEX20KE          ; Stratix       ;
; Create Debugging Nodes for IP Cores                                                        ; off               ; off           ;
; Disk space/compilation speed tradeoff                                                      ; Normal            ; Normal        ;
; Preserve fewer node names                                                                  ; On                ; On            ;
; Disable OpenCore Plus hardware evaluation                                                  ; Off               ; Off           ;
; Verilog Version                                                                            ; Verilog_2001      ; Verilog_2001  ;
; VHDL Version                                                                               ; VHDL93            ; VHDL93        ;
; Top-level entity name                                                                      ; control           ; control       ;
; State Machine Processing                                                                   ; Auto              ; Auto          ;
; NOT Gate Push-Back                                                                         ; On                ; On            ;
; Power-Up Don't Care                                                                        ; On                ; On            ;
; Remove Redundant Logic Cells                                                               ; Off               ; Off           ;
; Remove Duplicate Registers                                                                 ; On                ; On            ;
; Ignore CARRY Buffers                                                                       ; Off               ; Off           ;
; Ignore CASCADE Buffers                                                                     ; Off               ; Off           ;
; Ignore GLOBAL Buffers                                                                      ; Off               ; Off           ;
; Ignore ROW GLOBAL Buffers                                                                  ; Off               ; Off           ;
; Ignore LCELL Buffers                                                                       ; Off               ; Off           ;
; Ignore SOFT Buffers                                                                        ; On                ; On            ;
; Limit AHDL Integers to 32 Bits                                                             ; Off               ; Off           ;
; Auto Implement in ROM                                                                      ; Off               ; Off           ;
; Technology Mapper -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur              ; LUT               ; LUT           ;
; Optimization Technique -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur         ; Balanced          ; Balanced      ;
; Allow XOR Gate Usage                                                                       ; On                ; On            ;
; Carry Chain Length                                                                         ; 48                ; 48            ;
; Cascade Chain Length                                                                       ; 2                 ; 2             ;
; Parallel Expander Chain Length -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur ; 16                ; 16            ;
; Auto Carry Chains                                                                          ; On                ; On            ;
; Auto Parallel Expanders                                                                    ; On                ; On            ;
; Auto Open-Drain Pins                                                                       ; On                ; On            ;
; Remove Duplicate Logic                                                                     ; On                ; On            ;
; Perform WYSIWYG Primitive Resynthesis                                                      ; Off               ; Off           ;
; Perform gate-level register retiming                                                       ; Off               ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax                                     ; On                ; On            ;
; Auto ROM Replacement                                                                       ; On                ; On            ;
; Auto RAM Replacement                                                                       ; On                ; On            ;
; Auto Shift Register Replacement                                                            ; On                ; On            ;
; Auto Clock Enable Replacement                                                              ; On                ; On            ;
; Auto Resource Sharing                                                                      ; Off               ; Off           ;
; Allow Any RAM Size For Recognition                                                         ; Off               ; Off           ;
; Allow Any ROM Size For Recognition                                                         ; Off               ; Off           ;
; Allow Any Shift Register Size For Recognition                                              ; Off               ; Off           ;
+--------------------------------------------------------------------------------------------+-------------------+---------------+