📄 control.fit.rpt
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Fitter report for control
Thu Nov 11 05:12:14 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Floorplan View
7. Input Pins
8. Output Pins
9. All Package Pins
10. Control Signals
11. Global & Other Fast Signals
12. Non-Global High Fan-Out Signals
13. Local Routing Interconnect
14. MegaLAB Interconnect
15. LAB External Interconnect
16. MegaLAB Usage Summary
17. Row Interconnect
18. LAB Column Interconnect
19. ESB Column Interconnect
20. Fitter Resource Usage Summary
21. Fitter Resource Utilization by Entity
22. Delay Chain Summary
23. I/O Bank Usage
24. Pin-Out File
25. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+----------------------------------------------+
; Fitter Status ; Successful - Thu Nov 11 05:12:14 2004 ;
; Quartus II Version ; 4.1 Build 208 09/10/2004 SP 2 SJ Web Edition ;
; Revision Name ; control ;
; Top-level Entity Name ; control ;
; Family ; APEX20KE ;
; Device ; EP20K200EFC484-2X ;
; Timing Models ; Production ;
; Total logic elements ; 14 / 8,320 ( < 1 % ) ;
; Total pins ; 11 / 376 ( 2 % ) ;
; Total memory bits ; 0 / 106,496 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+----------------------------------------------+
+------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+--------------------+--------------------+
; Device ; EP20K200EFC484-2X ; ;
; SignalProbe signals routed during normal compilation ; Off ; Off ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Turbo Bit ; On ; On ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error ; On ;
; Release clears before tri-states ; Off ;
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/document/personal/inliverpool/VHDL/project/assignment1/module/control/control.fit.eqn.
+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-----------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; FastRow Interconnect ; I/O Standard ;
+-----------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; result[0] ; G4 ; J ; -- ; -- ; 1 ; no ; no ; yes ; no ; no ; no ; no ; LVTTL ;
; result[3] ; G5 ; J ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; result[5] ; K7 ; J ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; result[4] ; J4 ; J ; -- ; -- ; 1 ; no ; no ; yes ; no ; no ; no ; no ; LVTTL ;
; result[1] ; J22 ; J ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; result[2] ; G14 ; -- ; 2 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; num_re ; P19 ; P ; -- ; -- ; 3 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; clk ; N4 ; -- ; -- ; -- ; 4 ; yes ; no ; no ; no ; no ; no ; no ; LVTTL ;
; stop ; J18 ; N ; -- ; -- ; 1 ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
; reset ; R5 ; N ; -- ; -- ; 1 ; no ; no ; yes ; no ; no ; no ; no ; LVTTL ;
+-----------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; I/O Standard ;
+------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+--------------+
; RE ; T17 ; U ; -- ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL ;
+------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+--------------+
+-----------------------------------+
; All Package Pins ;
+-------+------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; A1 ; GND ; ;
; A2 ; GND* ; ;
; A3 ; GND* ; ;
; A4 ; GND* ; ;
; A5 ; GND* ; ;
; A6 ; GND* ; ;
; A7 ; GND* ; ;
; A8 ; GND* ; ;
; A9 ; NC ; ;
; A10 ; NC ; ;
; A11 ; GND ; ;
; A12 ; NC ; ;
; A13 ; NC ; ;
; A14 ; NC ; ;
; A15 ; GND* ; ;
; A16 ; GND* ; ;
; A17 ; GND* ; ;
; A18 ; GND* ; ;
; A19 ; GND* ; ;
; A20 ; GND* ; ;
; A21 ; GND* ; ;
; A22 ; GND ; ;
; B1 ; VCC_INT ; ;
; B2 ; GND ; ;
; B3 ; GND* ; ;
; B4 ; GND* ; ;
; B5 ; GND* ; ;
; B6 ; GND* ; ;
; B7 ; GND* ; ;
; B8 ; GND* ; ;
; B9 ; GND* ; ;
; B10 ; GND* ; ;
; B11 ; GND* ; ;
; B12 ; GND* ; ;
; B13 ; GND* ; ;
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