📄 buffer_display.tan.rpt
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+------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A ; None ; -4.029 ns ; RE ; p_state[1] ; clk ;
; N/A ; None ; -4.042 ns ; RE ; p_state[2] ; clk ;
; N/A ; None ; -4.675 ns ; done ; p_state[0] ; clk ;
; N/A ; None ; -4.754 ns ; done ; p_state[2] ; clk ;
; N/A ; None ; -5.250 ns ; RE ; p_state[0] ; clk ;
+---------------+-------------+-----------+------+------------+----------+
+-----------------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+------------+-----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------------+-----------+------------+
; N/A ; None ; 9.580 ns ; p_state[0] ; dout1[2] ; clk ;
; N/A ; None ; 9.584 ns ; p_state[0] ; dout1[1] ; clk ;
; N/A ; None ; 10.134 ns ; p_state[1] ; dout1[2] ; clk ;
; N/A ; None ; 10.138 ns ; p_state[1] ; dout1[1] ; clk ;
; N/A ; None ; 10.220 ns ; p_state[2] ; dout1[2] ; clk ;
; N/A ; None ; 10.224 ns ; p_state[2] ; dout1[1] ; clk ;
; N/A ; None ; 10.346 ns ; p_state[2] ; start ; clk ;
; N/A ; None ; 10.501 ns ; p_state[0] ; start ; clk ;
; N/A ; None ; 10.620 ns ; p_state[1] ; start ; clk ;
; N/A ; None ; 11.308 ns ; p_state[0] ; dout10[1] ; clk ;
; N/A ; None ; 11.608 ns ; p_state[0] ; dout1[0] ; clk ;
; N/A ; None ; 11.700 ns ; p_state[0] ; dout1[3] ; clk ;
; N/A ; None ; 11.719 ns ; p_state[0] ; dout10[3] ; clk ;
; N/A ; None ; 11.737 ns ; p_state[0] ; dout10[0] ; clk ;
; N/A ; None ; 11.862 ns ; p_state[1] ; dout10[1] ; clk ;
; N/A ; None ; 11.948 ns ; p_state[2] ; dout10[1] ; clk ;
; N/A ; None ; 12.162 ns ; p_state[1] ; dout1[0] ; clk ;
; N/A ; None ; 12.248 ns ; p_state[2] ; dout1[0] ; clk ;
; N/A ; None ; 12.254 ns ; p_state[1] ; dout1[3] ; clk ;
; N/A ; None ; 12.273 ns ; p_state[1] ; dout10[3] ; clk ;
; N/A ; None ; 12.291 ns ; p_state[1] ; dout10[0] ; clk ;
; N/A ; None ; 12.340 ns ; p_state[2] ; dout1[3] ; clk ;
; N/A ; None ; 12.359 ns ; p_state[2] ; dout10[3] ; clk ;
; N/A ; None ; 12.367 ns ; p_state[0] ; dout10[2] ; clk ;
; N/A ; None ; 12.377 ns ; p_state[2] ; dout10[0] ; clk ;
; N/A ; None ; 12.921 ns ; p_state[1] ; dout10[2] ; clk ;
; N/A ; None ; 13.007 ns ; p_state[2] ; dout10[2] ; clk ;
+---------------+------------------+----------------+------------+-----------+------------+
+----------------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+----------+-----------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+----------+-----------+
; N/A ; None ; 8.560 ns ; din1[1] ; dout1[1] ;
; N/A ; None ; 9.251 ns ; din1[2] ; dout1[2] ;
; N/A ; None ; 10.677 ns ; din1[3] ; dout1[3] ;
; N/A ; None ; 12.754 ns ; RE ; dout1[2] ;
; N/A ; None ; 12.758 ns ; RE ; dout1[1] ;
; N/A ; None ; 13.023 ns ; din10[0] ; dout10[0] ;
; N/A ; None ; 13.218 ns ; din1[0] ; dout1[0] ;
; N/A ; None ; 13.609 ns ; din10[3] ; dout10[3] ;
; N/A ; None ; 13.792 ns ; din10[2] ; dout10[2] ;
; N/A ; None ; 14.482 ns ; RE ; dout10[1] ;
; N/A ; None ; 14.752 ns ; din10[1] ; dout10[1] ;
; N/A ; None ; 14.782 ns ; RE ; dout1[0] ;
; N/A ; None ; 14.874 ns ; RE ; dout1[3] ;
; N/A ; None ; 14.893 ns ; RE ; dout10[3] ;
; N/A ; None ; 14.911 ns ; RE ; dout10[0] ;
; N/A ; None ; 15.541 ns ; RE ; dout10[2] ;
+---------------+-------------------+-----------------+----------+-----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
Info: Processing started: Thu Nov 04 05:09:28 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off buffer_display -c buffer_display
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register p_state[2] and destination register p_state[1]
Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.761 ns
Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state[2]'
Info: 2: + IC(0.398 ns) + CELL(1.139 ns) = 1.746 ns; Loc. = LC5_8_G2; Fanout = 1; COMB Node = 'start$latch$en_or'
Info: 3: + IC(0.356 ns) + CELL(0.659 ns) = 2.761 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state[1]'
Info: Total cell delay = 2.007 ns ( 72.69 % )
Info: Total interconnect delay = 0.754 ns ( 27.31 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clk to destination register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state[1]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: - Longest clock path from clock clk to source register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state[2]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: + Micro clock to output delay of source is 0.434 ns
Info: + Micro setup delay of destination is 0.164 ns
Info: tsu for register p_state[0] (data pin = RE, clock pin = clk) is 5.763 ns
Info: + Longest pin to register delay is 8.339 ns
Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'
Info: 2: + IC(4.452 ns) + CELL(0.899 ns) = 7.172 ns; Loc. = LC2_8_G2; Fanout = 1; COMB Node = 'n_state[0]~311'
Info: 3: + IC(0.000 ns) + CELL(0.689 ns) = 7.861 ns; Loc. = LC3_8_G2; Fanout = 1; COMB Node = 'n_state[0]~313'
Info: 4: + IC(0.284 ns) + CELL(0.194 ns) = 8.339 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state[0]'
Info: Total cell delay = 3.603 ns ( 43.21 % )
Info: Total interconnect delay = 4.736 ns ( 56.79 % )
Info: + Micro setup delay of destination is 0.164 ns
Info: - Shortest clock path from clock clk to destination register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state[0]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: tco from clock clk to destination pin dout10[1] through register p_state[2] is 15.021 ns
Info: + Longest clock path from clock clk to source register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state[2]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: + Micro clock to output delay of source is 0.434 ns
Info: + Longest register to pin delay is 11.847 ns
Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state[2]'
Info: 2: + IC(0.398 ns) + CELL(1.139 ns) = 1.746 ns; Loc. = LC9_8_G2; Fanout = 16; COMB Node = 'comb~321'
Info: 3: + IC(1.264 ns) + CELL(1.139 ns) = 4.149 ns; Loc. = LC3_6_G2; Fanout = 2; COMB Node = '\comb:store10[1]~73'
Info: 4: + IC(0.303 ns) + CELL(0.464 ns) = 4.916 ns; Loc. = LC5_6_G2; Fanout = 1; COMB Node = 'comb~326'
Info: 5: + IC(0.300 ns) + CELL(1.034 ns) = 6.250 ns; Loc. = LC6_7_G2; Fanout = 2; COMB Node = 'dout10[1]$latch~133'
Info: 6: + IC(3.031 ns) + CELL(2.566 ns) = 11.847 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'dout10[1]'
Info: Total cell delay = 6.551 ns ( 55.30 % )
Info: Total interconnect delay = 5.296 ns ( 44.70 % )
Info: Longest tpd from source pin RE to destination pin dout10[1] is 17.556 ns
Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'
Info: 2: + IC(4.480 ns) + CELL(1.154 ns) = 7.455 ns; Loc. = LC9_8_G2; Fanout = 16; COMB Node = 'comb~321'
Info: 3: + IC(1.264 ns) + CELL(1.139 ns) = 9.858 ns; Loc. = LC3_6_G2; Fanout = 2; COMB Node = '\comb:store10[1]~73'
Info: 4: + IC(0.303 ns) + CELL(0.464 ns) = 10.625 ns; Loc. = LC5_6_G2; Fanout = 1; COMB Node = 'comb~326'
Info: 5: + IC(0.300 ns) + CELL(1.034 ns) = 11.959 ns; Loc. = LC6_7_G2; Fanout = 2; COMB Node = 'dout10[1]$latch~133'
Info: 6: + IC(3.031 ns) + CELL(2.566 ns) = 17.556 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'dout10[1]'
Info: Total cell delay = 8.178 ns ( 46.58 % )
Info: Total interconnect delay = 9.378 ns ( 53.42 % )
Info: th for register p_state[1] (data pin = RE, clock pin = clk) is -4.029 ns
Info: + Longest clock path from clock clk to destination register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state[1]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: + Micro hold delay of destination is 0.349 ns
Info: - Shortest pin to register delay is 7.118 ns
Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'
Info: 2: + IC(4.508 ns) + CELL(0.789 ns) = 7.118 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state[1]'
Info: Total cell delay = 2.610 ns ( 36.67 % )
Info: Total interconnect delay = 4.508 ns ( 63.33 % )
Info: Minimum tco from clock clk to destination pin dout1[2] through register p_state[0] is 9.580 ns
Info: + Shortest clock path from clock clk to source register is 2.740 ns
Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state[0]'
Info: Total cell delay = 1.373 ns ( 50.11 % )
Info: Total interconnect delay = 1.367 ns ( 49.89 % )
Info: + Micro clock to output delay of source is 0.434 ns
Info: + Shortest register to pin delay is 6.406 ns
Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state[0]'
Info: 2: + IC(0.433 ns) + CELL(0.464 ns) = 1.106 ns; Loc. = LC7_8_G2; Fanout = 8; COMB Node = 'comb~324'
Info: 3: + IC(1.408 ns) + CELL(1.034 ns) = 3.548 ns; Loc. = LC3_1_G2; Fanout = 2; COMB Node = 'dout1[2]$latch~133'
Info: 4: + IC(0.292 ns) + CELL(2.566 ns) = 6.406 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'dout1[2]'
Info: Total cell delay = 4.273 ns ( 66.70 % )
Info: Total interconnect delay = 2.133 ns ( 33.30 % )
Info: Shortest tpd from source pin din1[1] to destination pin dout1[1] is 8.560 ns
Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_E20; Fanout = 2; PIN Node = 'din1[1]'
Info: 2: + IC(2.134 ns) + CELL(1.034 ns) = 4.914 ns; Loc. = LC5_1_G2; Fanout = 1; COMB Node = 'comb~330'
Info: 3: + IC(0.324 ns) + CELL(0.464 ns) = 5.702 ns; Loc. = LC4_1_G2; Fanout = 2; COMB Node = 'dout1[1]$latch~133'
Info: 4: + IC(0.292 ns) + CELL(2.566 ns) = 8.560 ns; Loc. = PIN_E22; Fanout = 0; PIN Node = 'dout1[1]'
Info: Total cell delay = 5.810 ns ( 67.87 % )
Info: Total interconnect delay = 2.750 ns ( 32.13 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Nov 04 05:09:30 2004
Info: Elapsed time: 00:00:02
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