📄 buffer_display.tan.rpt
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Timing Analyzer report for buffer_display
Thu Nov 04 05:09:30 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Minimum tco
11. Minimum tpd
12. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP20K200EFC484-2X ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.763 ns ; RE ; p_state[0] ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 15.021 ns ; p_state[2] ; dout10[1] ; clk ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 17.556 ns ; RE ; dout10[1] ; ; ; 0 ;
; Worst-case th ; N/A ; None ; -4.029 ns ; RE ; p_state[1] ; ; clk ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 9.580 ns ; p_state[0] ; dout1[2] ; clk ; ; 0 ;
; Worst-case Minimum tpd ; N/A ; None ; 8.560 ns ; din1[1] ; dout1[1] ; ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[2] ; p_state[1] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[2] ; p_state[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[1] ; p_state[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[2] ; p_state[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[1] ; p_state[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[2] ; p_state[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[1] ; p_state[2] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[0] ; p_state[1] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[0] ; p_state[0] ; clk ; clk ; None ; None ; None ;
; N/A ; Restricted to 233.64 MHz ( period = 4.280 ns ) ; p_state[0] ; p_state[2] ; clk ; clk ; None ; None ; None ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+------------+----------+
; N/A ; None ; 5.763 ns ; RE ; p_state[0] ; clk ;
; N/A ; None ; 5.267 ns ; done ; p_state[2] ; clk ;
; N/A ; None ; 5.188 ns ; done ; p_state[0] ; clk ;
; N/A ; None ; 4.555 ns ; RE ; p_state[2] ; clk ;
; N/A ; None ; 4.542 ns ; RE ; p_state[1] ; clk ;
+-------+--------------+------------+------+------------+----------+
+-------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------+-----------+------------+
; N/A ; None ; 15.021 ns ; p_state[2] ; dout10[1] ; clk ;
; N/A ; None ; 14.935 ns ; p_state[1] ; dout10[1] ; clk ;
; N/A ; None ; 14.891 ns ; p_state[0] ; dout10[1] ; clk ;
; N/A ; None ; 14.607 ns ; p_state[2] ; dout10[2] ; clk ;
; N/A ; None ; 14.521 ns ; p_state[1] ; dout10[2] ; clk ;
; N/A ; None ; 14.477 ns ; p_state[0] ; dout10[2] ; clk ;
; N/A ; None ; 14.044 ns ; p_state[2] ; dout1[3] ; clk ;
; N/A ; None ; 13.978 ns ; p_state[2] ; dout10[0] ; clk ;
; N/A ; None ; 13.958 ns ; p_state[1] ; dout1[3] ; clk ;
; N/A ; None ; 13.927 ns ; p_state[2] ; dout10[3] ; clk ;
; N/A ; None ; 13.892 ns ; p_state[1] ; dout10[0] ; clk ;
; N/A ; None ; 13.877 ns ; p_state[2] ; dout1[0] ; clk ;
; N/A ; None ; 13.841 ns ; p_state[1] ; dout10[3] ; clk ;
; N/A ; None ; 13.835 ns ; p_state[0] ; dout10[0] ; clk ;
; N/A ; None ; 13.812 ns ; p_state[0] ; dout10[3] ; clk ;
; N/A ; None ; 13.799 ns ; p_state[0] ; dout1[3] ; clk ;
; N/A ; None ; 13.791 ns ; p_state[1] ; dout1[0] ; clk ;
; N/A ; None ; 13.732 ns ; p_state[0] ; dout1[0] ; clk ;
; N/A ; None ; 12.624 ns ; p_state[2] ; dout1[2] ; clk ;
; N/A ; None ; 12.538 ns ; p_state[1] ; dout1[2] ; clk ;
; N/A ; None ; 12.374 ns ; p_state[0] ; dout1[2] ; clk ;
; N/A ; None ; 11.925 ns ; p_state[2] ; dout1[1] ; clk ;
; N/A ; None ; 11.839 ns ; p_state[1] ; dout1[1] ; clk ;
; N/A ; None ; 11.695 ns ; p_state[0] ; dout1[1] ; clk ;
; N/A ; None ; 10.620 ns ; p_state[1] ; start ; clk ;
; N/A ; None ; 10.501 ns ; p_state[0] ; start ; clk ;
; N/A ; None ; 10.346 ns ; p_state[2] ; start ; clk ;
+-------+--------------+------------+------------+-----------+------------+
+--------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+----------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+----------+-----------+
; N/A ; None ; 17.556 ns ; RE ; dout10[1] ;
; N/A ; None ; 17.142 ns ; RE ; dout10[2] ;
; N/A ; None ; 16.579 ns ; RE ; dout1[3] ;
; N/A ; None ; 16.513 ns ; RE ; dout10[0] ;
; N/A ; None ; 16.462 ns ; RE ; dout10[3] ;
; N/A ; None ; 16.412 ns ; RE ; dout1[0] ;
; N/A ; None ; 15.435 ns ; din10[1] ; dout10[1] ;
; N/A ; None ; 15.159 ns ; RE ; dout1[2] ;
; N/A ; None ; 14.558 ns ; din10[2] ; dout10[2] ;
; N/A ; None ; 14.460 ns ; RE ; dout1[1] ;
; N/A ; None ; 14.370 ns ; din10[3] ; dout10[3] ;
; N/A ; None ; 13.914 ns ; din1[0] ; dout1[0] ;
; N/A ; None ; 13.805 ns ; din10[0] ; dout10[0] ;
; N/A ; None ; 11.476 ns ; din1[3] ; dout1[3] ;
; N/A ; None ; 10.050 ns ; din1[2] ; dout1[2] ;
; N/A ; None ; 9.335 ns ; din1[1] ; dout1[1] ;
+-------+-------------------+-----------------+----------+-----------+
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