buffer_display.tan.qmsg

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键

{ "Info" "ITDB_FULL_TPD_RESULT" "din1\[1\] dout1\[1\] 8.560 ns Shortest " "Info: Shortest tpd from source pin din1\[1\] to destination pin dout1\[1\] is 8.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.746 ns) 1.746 ns din1\[1\] 1 PIN PIN_E20 2 " "Info: 1: + IC(0.000 ns) + CELL(1.746 ns) = 1.746 ns; Loc. = PIN_E20; Fanout = 2; PIN Node = 'din1\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { din1[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.134 ns) + CELL(1.034 ns) 4.914 ns comb~330 2 COMB LC5_1_G2 1 " "Info: 2: + IC(2.134 ns) + CELL(1.034 ns) = 4.914 ns; Loc. = LC5_1_G2; Fanout = 1; COMB Node = 'comb~330'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "3.168 ns" { din1[1] comb~330 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.464 ns) 5.702 ns dout1\[1\]\$latch~133 3 COMB LC4_1_G2 2 " "Info: 3: + IC(0.324 ns) + CELL(0.464 ns) = 5.702 ns; Loc. = LC4_1_G2; Fanout = 2; COMB Node = 'dout1\[1\]\$latch~133'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.788 ns" { comb~330 dout1[1]$latch~133 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(2.566 ns) 8.560 ns dout1\[1\] 4 PIN PIN_E22 0 " "Info: 4: + IC(0.292 ns) + CELL(2.566 ns) = 8.560 ns; Loc. = PIN_E22; Fanout = 0; PIN Node = 'dout1\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.858 ns" { dout1[1]$latch~133 dout1[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.810 ns 67.87 % " "Info: Total cell delay = 5.810 ns ( 67.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.750 ns 32.13 % " "Info: Total interconnect delay = 2.750 ns ( 32.13 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "8.560 ns" { din1[1] comb~330 dout1[1]$latch~133 dout1[1] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 04 05:09:30 2004 " "Info: Processing ended: Thu Nov 04 05:09:30 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}