buffer_display.tan.qmsg

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout10\[1\] p_state\[2\] 15.021 ns register " "Info: tco from clock clk to destination pin dout10\[1\] through register p_state\[2\] is 15.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[2\] 2 REG LC10_8_G2 8 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.847 ns + Longest register pin " "Info: + Longest register to pin delay is 11.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[2\] 1 REG LC10_8_G2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(1.139 ns) 1.746 ns comb~321 2 COMB LC9_8_G2 16 " "Info: 2: + IC(0.398 ns) + CELL(1.139 ns) = 1.746 ns; Loc. = LC9_8_G2; Fanout = 16; COMB Node = 'comb~321'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.537 ns" { p_state[2] comb~321 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(1.139 ns) 4.149 ns \\comb:store10\[1\]~73 3 COMB LC3_6_G2 2 " "Info: 3: + IC(1.264 ns) + CELL(1.139 ns) = 4.149 ns; Loc. = LC3_6_G2; Fanout = 2; COMB Node = '\\comb:store10\[1\]~73'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.403 ns" { comb~321 \comb:store10[1]~73 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.464 ns) 4.916 ns comb~326 4 COMB LC5_6_G2 1 " "Info: 4: + IC(0.303 ns) + CELL(0.464 ns) = 4.916 ns; Loc. = LC5_6_G2; Fanout = 1; COMB Node = 'comb~326'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.767 ns" { \comb:store10[1]~73 comb~326 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.034 ns) 6.250 ns dout10\[1\]\$latch~133 5 COMB LC6_7_G2 2 " "Info: 5: + IC(0.300 ns) + CELL(1.034 ns) = 6.250 ns; Loc. = LC6_7_G2; Fanout = 2; COMB Node = 'dout10\[1\]\$latch~133'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.334 ns" { comb~326 dout10[1]$latch~133 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.031 ns) + CELL(2.566 ns) 11.847 ns dout10\[1\] 6 PIN PIN_M7 0 " "Info: 6: + IC(3.031 ns) + CELL(2.566 ns) = 11.847 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'dout10\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "5.597 ns" { dout10[1]$latch~133 dout10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.551 ns 55.30 % " "Info: Total cell delay = 6.551 ns ( 55.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.296 ns 44.70 % " "Info: Total interconnect delay = 5.296 ns ( 44.70 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "11.847 ns" { p_state[2] comb~321 \comb:store10[1]~73 comb~326 dout10[1]$latch~133 dout10[1] } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "11.847 ns" { p_state[2] comb~321 \comb:store10[1]~73 comb~326 dout10[1]$latch~133 dout10[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "RE dout10\[1\] 17.556 ns Longest " "Info: Longest tpd from source pin RE to destination pin dout10\[1\] is 17.556 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.821 ns) 1.821 ns RE 1 PIN PIN_D14 5 " "Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { RE } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.480 ns) + CELL(1.154 ns) 7.455 ns comb~321 2 COMB LC9_8_G2 16 " "Info: 2: + IC(4.480 ns) + CELL(1.154 ns) = 7.455 ns; Loc. = LC9_8_G2; Fanout = 16; COMB Node = 'comb~321'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "5.634 ns" { RE comb~321 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(1.139 ns) 9.858 ns \\comb:store10\[1\]~73 3 COMB LC3_6_G2 2 " "Info: 3: + IC(1.264 ns) + CELL(1.139 ns) = 9.858 ns; Loc. = LC3_6_G2; Fanout = 2; COMB Node = '\\comb:store10\[1\]~73'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.403 ns" { comb~321 \comb:store10[1]~73 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.464 ns) 10.625 ns comb~326 4 COMB LC5_6_G2 1 " "Info: 4: + IC(0.303 ns) + CELL(0.464 ns) = 10.625 ns; Loc. = LC5_6_G2; Fanout = 1; COMB Node = 'comb~326'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.767 ns" { \comb:store10[1]~73 comb~326 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.034 ns) 11.959 ns dout10\[1\]\$latch~133 5 COMB LC6_7_G2 2 " "Info: 5: + IC(0.300 ns) + CELL(1.034 ns) = 11.959 ns; Loc. = LC6_7_G2; Fanout = 2; COMB Node = 'dout10\[1\]\$latch~133'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.334 ns" { comb~326 dout10[1]$latch~133 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.031 ns) + CELL(2.566 ns) 17.556 ns dout10\[1\] 6 PIN PIN_M7 0 " "Info: 6: + IC(3.031 ns) + CELL(2.566 ns) = 17.556 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'dout10\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "5.597 ns" { dout10[1]$latch~133 dout10[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.178 ns 46.58 % " "Info: Total cell delay = 8.178 ns ( 46.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.378 ns 53.42 % " "Info: Total interconnect delay = 9.378 ns ( 53.42 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "17.556 ns" { RE comb~321 \comb:store10[1]~73 comb~326 dout10[1]$latch~133 dout10[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "p_state\[1\] RE clk -4.029 ns register " "Info: th for register p_state\[1\] (data pin = RE, clock pin = clk) is -4.029 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[1\] 2 REG LC4_8_G2 9 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.349 ns + " "Info: + Micro hold delay of destination is 0.349 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.118 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.821 ns) 1.821 ns RE 1 PIN PIN_D14 5 " "Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { RE } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.508 ns) + CELL(0.789 ns) 7.118 ns p_state\[1\] 2 REG LC4_8_G2 9 " "Info: 2: + IC(4.508 ns) + CELL(0.789 ns) = 7.118 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state\[1\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "5.297 ns" { RE p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.610 ns 36.67 % " "Info: Total cell delay = 2.610 ns ( 36.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.508 ns 63.33 % " "Info: Total interconnect delay = 4.508 ns ( 63.33 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "7.118 ns" { RE p_state[1] } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "7.118 ns" { RE p_state[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dout1\[2\] p_state\[0\] 9.580 ns register " "Info: Minimum tco from clock clk to destination pin dout1\[2\] through register p_state\[0\] is 9.580 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[0\] 2 REG LC8_8_G2 9 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.406 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[0\] 1 REG LC8_8_G2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.464 ns) 1.106 ns comb~324 2 COMB LC7_8_G2 8 " "Info: 2: + IC(0.433 ns) + CELL(0.464 ns) = 1.106 ns; Loc. = LC7_8_G2; Fanout = 8; COMB Node = 'comb~324'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.897 ns" { p_state[0] comb~324 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.408 ns) + CELL(1.034 ns) 3.548 ns dout1\[2\]\$latch~133 3 COMB LC3_1_G2 2 " "Info: 3: + IC(1.408 ns) + CELL(1.034 ns) = 3.548 ns; Loc. = LC3_1_G2; Fanout = 2; COMB Node = 'dout1\[2\]\$latch~133'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.442 ns" { comb~324 dout1[2]$latch~133 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.292 ns) + CELL(2.566 ns) 6.406 ns dout1\[2\] 4 PIN PIN_G20 0 " "Info: 4: + IC(0.292 ns) + CELL(2.566 ns) = 6.406 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'dout1\[2\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.858 ns" { dout1[2]$latch~133 dout1[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.273 ns 66.70 % " "Info: Total cell delay = 4.273 ns ( 66.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.133 ns 33.30 % " "Info: Total interconnect delay = 2.133 ns ( 33.30 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "6.406 ns" { p_state[0] comb~324 dout1[2]$latch~133 dout1[2] } "NODE_NAME" } } }  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "6.406 ns" { p_state[0] comb~324 dout1[2]$latch~133 dout1[2] } "NODE_NAME" } } }  } 0}