📄 buffer_display.tan.qmsg
字号:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } } { "c:/altera/quartus41sp2/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register p_state\[2\] p_state\[1\] 233.64 MHz Internal " "Info: Clock clk Internal fmax is restricted to 233.64 MHz between source register p_state\[2\] and destination register p_state\[1\]" { { "Info" "ITDB_CLOCK_RATE" "clock 4.28 ns " "Info: fmax restricted to clock pin edge rate 4.28 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.761 ns + Longest register register " "Info: + Longest register to register delay is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[2\] 1 REG LC10_8_G2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(1.139 ns) 1.746 ns start\$latch\$en_or 2 COMB LC5_8_G2 1 " "Info: 2: + IC(0.398 ns) + CELL(1.139 ns) = 1.746 ns; Loc. = LC5_8_G2; Fanout = 1; COMB Node = 'start\$latch\$en_or'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.537 ns" { p_state[2] start$latch$en_or } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.659 ns) 2.761 ns p_state\[1\] 3 REG LC4_8_G2 9 " "Info: 3: + IC(0.356 ns) + CELL(0.659 ns) = 2.761 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.015 ns" { start$latch$en_or p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.007 ns 72.69 % " "Info: Total cell delay = 2.007 ns ( 72.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.754 ns 27.31 % " "Info: Total interconnect delay = 0.754 ns ( 27.31 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.761 ns" { p_state[2] start$latch$en_or p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[1\] 2 REG LC4_8_G2 9 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC4_8_G2; Fanout = 9; REG Node = 'p_state\[1\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[2\] 2 REG LC10_8_G2 8 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC10_8_G2; Fanout = 8; REG Node = 'p_state\[2\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[2] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.434 ns + " "Info: + Micro clock to output delay of source is 0.434 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.761 ns" { p_state[2] start$latch$en_or p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[2] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { p_state[1] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "p_state\[0\] RE clk 5.763 ns register " "Info: tsu for register p_state\[0\] (data pin = RE, clock pin = clk) is 5.763 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.339 ns + Longest pin register " "Info: + Longest pin to register delay is 8.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.821 ns) 1.821 ns RE 1 PIN PIN_D14 5 " "Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_D14; Fanout = 5; PIN Node = 'RE'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { RE } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.452 ns) + CELL(0.899 ns) 7.172 ns n_state\[0\]~311 2 COMB LC2_8_G2 1 " "Info: 2: + IC(4.452 ns) + CELL(0.899 ns) = 7.172 ns; Loc. = LC2_8_G2; Fanout = 1; COMB Node = 'n_state\[0\]~311'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "5.351 ns" { RE n_state[0]~311 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.689 ns) 7.861 ns n_state\[0\]~313 3 COMB LC3_8_G2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.689 ns) = 7.861 ns; Loc. = LC3_8_G2; Fanout = 1; COMB Node = 'n_state\[0\]~313'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.689 ns" { n_state[0]~311 n_state[0]~313 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.194 ns) 8.339 ns p_state\[0\] 4 REG LC8_8_G2 9 " "Info: 4: + IC(0.284 ns) + CELL(0.194 ns) = 8.339 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.478 ns" { n_state[0]~313 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.603 ns 43.21 % " "Info: Total cell delay = 3.603 ns ( 43.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.736 ns 56.79 % " "Info: Total interconnect delay = 4.736 ns ( 56.79 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "8.339 ns" { RE n_state[0]~311 n_state[0]~313 p_state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.164 ns + " "Info: + Micro setup delay of destination is 0.164 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.373 ns) 1.373 ns clk 1 CLK PIN_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_N4; Fanout = 3; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.000 ns) 2.740 ns p_state\[0\] 2 REG LC8_8_G2 9 " "Info: 2: + IC(1.367 ns) + CELL(0.000 ns) = 2.740 ns; Loc. = LC8_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.367 ns" { clk p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 50.11 % " "Info: Total cell delay = 1.373 ns ( 50.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.367 ns 49.89 % " "Info: Total interconnect delay = 1.367 ns ( 49.89 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "8.339 ns" { RE n_state[0]~311 n_state[0]~313 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "2.740 ns" { clk p_state[0] } "NODE_NAME" } } } } 0}
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