buffer_display.fit.qmsg

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 04 05:09:13 2004 " "Info: Processing started: Thu Nov 04 05:09:13 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off buffer_display -c buffer_display " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off buffer_display -c buffer_display" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "buffer_display EP20K200EFC484-2X " "Info: Selected device EP20K200EFC484-2X for design buffer_display" {  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "SignalProbe " "Warning: Feature SignalProbe is not available with your current license" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell clk to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "reset automatically " "Info: Promoted cell reset to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Thu Nov 04 2004 05:09:16 " "Info: Started fitting attempt 1 on Thu Nov 04 2004 at 05:09:16" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "1 " "Info: Maximum column FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "5 " "Info: Maximum row FastTrack interconnect = 5%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.264 ns register register " "Info: Estimated most critical path is register to register delay of 3.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns p_state\[0\] 1 REG LAB_8_G2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LAB_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "" { p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.899 ns) 1.392 ns n_state\[0\]~311 2 COMB LAB_8_G2 1 " "Info: 2: + IC(0.284 ns) + CELL(0.899 ns) = 1.392 ns; Loc. = LAB_8_G2; Fanout = 1; COMB Node = 'n_state\[0\]~311'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.183 ns" { p_state[0] n_state[0]~311 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.689 ns) 2.081 ns n_state\[0\]~313 3 COMB LAB_8_G2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.689 ns) = 2.081 ns; Loc. = LAB_8_G2; Fanout = 1; COMB Node = 'n_state\[0\]~313'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "0.689 ns" { n_state[0]~311 n_state[0]~313 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.899 ns) 3.264 ns p_state\[0\] 4 REG LAB_8_G2 9 " "Info: 4: + IC(0.284 ns) + CELL(0.899 ns) = 3.264 ns; Loc. = LAB_8_G2; Fanout = 9; REG Node = 'p_state\[0\]'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "1.183 ns" { n_state[0]~313 p_state[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.696 ns 82.60 % " "Info: Total cell delay = 2.696 ns ( 82.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.568 ns 17.40 % " "Info: Total interconnect delay = 0.568 ns ( 17.40 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display_cmp.qrpt" Compiler "buffer_display" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/db/buffer_display.quartus_db" { Floorplan "" "" "3.264 ns" { p_state[0] n_state[0]~311 n_state[0]~313 p_state[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "4 " "Info: Fitter routing operations ending: elapsed time = 4 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 04 05:09:22 2004 " "Info: Processing ended: Thu Nov 04 05:09:22 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}