buffer_display.map.rpt

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键

; Hierarchy ;
+-----------+
buffer_display


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |buffer_display            ; 35 (35)     ; 3            ; 0           ; 21   ; 0            ; 32 (32)      ; 2 (2)             ; 1 (1)            ; 0 (0)           ; |buffer_display     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------+-------------------+
; File Name          ; Used in Netlist   ;
+--------------------+-------------------+
; buffer_display.vhd ; yes               ;
+--------------------+-------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 35        ;
; Total combinational functions   ; 33        ;
; Total 4-input functions         ; 15        ;
; Total 3-input functions         ; 18        ;
; Total 2-input functions         ; 0         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 3         ;
; I/O pins                        ; 21        ;
; Maximum fan-out node            ; comb~321  ;
; Maximum fan-out                 ; 16        ;
; Total fan-out                   ; 133       ;
; Average fan-out                 ; 2.38      ;
+---------------------------------+-----------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 17    ;
; Number of synthesis-generated cells                    ; 18    ;
; Number of WYSIWYG LUTs                                 ; 17    ;
; Number of synthesis-generated LUTs                     ; 16    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 3     ;
; Number of cells with combinational logic only          ; 32    ;
; Number of cells with registers only                    ; 2     ;
; Number of cells with combinational logic and registers ; 1     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 3     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Thu Nov 04 05:09:10 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off buffer_display -c buffer_display
Info: Found 2 design units, including 1 entities, in source file buffer_display.vhd
    Info: Found design unit 1: buffer_display-buffer_display_architecture
    Info: Found entity 1: buffer_display
Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable start may not be assigned a new value in every possible path through the Process Statement. Signal or variable start holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable dout10 may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout10 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable dout1 may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable store10 may not be assigned a new value in every possible path through the Process Statement. Signal or variable store10 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable store1 may not be assigned a new value in every possible path through the Process Statement. Signal or variable store1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 17 buffer(s)
    Info: Ignored 17 SOFT buffer(s)
Warning: Feature Netlist Optimizations is not available with your current license
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 56 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 9 output pins
    Info: Implemented 35 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Thu Nov 04 05:09:12 2004
    Info: Elapsed time: 00:00:01