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<HTML><HEAD><TITLE>A one bit DAC that use pulse modulation</TITLE></HEAD><BODY bgcolor="#ffffff" <CENTER><hr size=5><h3>A one bit DAC that use pulse modulation</h3><p><hr size=5><p><pre><i>// *********************************************************// *// * 1-bit DAC// *// * file = dac3.v// *// * Bill Seiler// * Circuit City / Patapsco West // * 12/30/96 bjs created// * 01/14/97 bjs use assign for dac// *// *********************************************************module dac(resetl, clk, val, dac_out) ;input resetl ;input clk ;input [7:0] val ;output dac_out ;wire clk ;wire [7:0] val ;reg [7:0] dac_ctr ;wire dac_out ;always @(posedge clk or negedge resetl) if (!resetl) dac_ctr[7:0] = 8'b0 ; else dac_ctr[7:0] = dac_ctr[7:0] + 1 ; assign dac_out = (val[7] & dac_ctr[0]) | (val[6] & dac_ctr[1] & ~dac_ctr[0]) | (val[5] & dac_ctr[2] & ~dac_ctr[1] & ~dac_ctr[0]) | (val[4] & dac_ctr[3] & ~dac_ctr[2] & ~dac_ctr[1] &~dac_ctr[0]) | (val[3] & dac_ctr[4] & ~dac_ctr[3] & ~dac_ctr[2] &~dac_ctr[1] & ~dac_ctr[0]) | (val[2] & dac_ctr[5] & ~dac_ctr[4] & ~dac_ctr[3] &~dac_ctr[2] & ~dac_ctr[1] & ~dac_ctr[0]) | (val[1] & dac_ctr[6] & ~dac_ctr[5] & ~dac_ctr[4] &~dac_ctr[3] & ~dac_ctr[2] & ~dac_ctr[1] & ~dac_ctr[0]) | (val[0] & dac_ctr[7] & ~dac_ctr[6] & ~dac_ctr[5] &~dac_ctr[4] & ~dac_ctr[3] & ~dac_ctr[2] & ~dac_ctr[1] & ~dac_ctr[0]) ;endmodule</i></pre><hr size=5><A HREF="ver_eda.html"><IMG SRC="thbeda.gif" ALT="BACK" BORDER=0> Back to Celia's Verilog Page</a></BODY></HTML>⌨️ 快捷键说明
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