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<HTML><HEAD><TITLE>Writing counters for Synopsys synthesis...</TITLE></HEAD><BODY bgcolor="#ffffff" <CENTER><hr size=5><h3>Writing counters for Synopsys synthesis...</h3><p><hr size=5><p>Writing counters that are compact and meet your timing requirements canbe somewhat tricky. There are several approaches that you will want to look at. Depending on your area and speed requirements and on the contents of you vendor library, you will want to try radically differentapproaches.<p>If you are trying to get a fast counter for a specific IC library, yourbest bet is to check if you vendor has counter cell that you can use. Thesewill always end up being faster, since they are hand optimized for oneparticular library. If library independence is important, you will have to create your own counter. The easiest way, of course, is simple count = count + 1. Unfortunately, this will probably not give youthe best results. Sometimes, I have found that smaller counters compiledbetter using a sequencer methodology. <p><pre><i>For example:always @(count) case (count) // synopsys full_case parallel_case 2'h0: next_count = 2'h1; 2'h1: next_count = 2'h2; 2'h2: next_count = 2'h3; 2'h3: next_count = 2'h0; endcaseendalways @ (posedge clk or posedge reset)begin if (reset) begin count = 0; end else if (enable) begin count = next_count; endend</i></pre>If you are not going to have your count value ready within one clockcycle you can use a safe method of asynchronously generating thecount enable. The constraint is that enable must be a glitch free signal and must have the proper timing in relationship to the clock.<p><pre><i>For example:wire gate_clk = clk & enable;always @ (posedge gate_clk or posedge reset)begin if (reset) begin count = 0; end else begin count = count + 1; endend</i></pre><p>Synopsys uses designware to implement counters, adders, comparators, etc..You can control the type of designware function used by inserting compilerdirectives into your code. For example, the increment function canuse ripple carry or carry look ahead. You may want to force a particularimplementation.<pre><i>An example: This will force a DW01_inc block to be implemented as a carry look ahead incrementeralways @ (posedge clk or posedge reset)begin : b1 /* synopsys resource r0: map_to_module = "DW01_inc", implementation = "cla", ops = "inc1"; */ if (reset) begin count = 0; end else if (enable) begin count = count + 1; // synopsys label inc1 endend</i></pre>Another type of counter is the ripple counter. You can generate onein verilog quite easily and it can be good for slow, low power applications.<p><pre><i>For example:always @(count) begin count0 = count[0] ; count1 = count[1] ; count2 = count[2] ;endalways @(posedge clk or posedge reset) begin if (reset) begin count[0] = 0 ; end else begin count[0] = ~count[0]; endendalways @(posedge count0 or posedge reset)begin if (reset) begin count[1] = 0 ; end else begin count[1] = ~count[1]; endendalways @(posedge count1 or posedge reset)begin if (reset) begin count[2] = 0 ; end else begin count[2] = ~count[2]; endendalways @(posedge count2 or posedge reset)begin if (reset) begin count[3] = 0 ; end else begin count[3] = ~count[3]; endend</i></pre><hr size=5></BODY></HTML>⌨️ 快捷键说明
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