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<HTML><HEAD><TITLE>A 16 bit shift register</TITLE></HEAD><BODY bgcolor="#ffffff" <CENTER><hr size=5><h3>A 16 bit shift register</h3><p><hr size=5><p><pre><i>/******************************************************************************** AUTHOR: Celia Clause*-------------------------* Copyright September 1997********************************************************************************** REVISION HISTORY* ----------------* $Revision$* $Log$*********************************************************************************** Module shift_register-- This block of code will generate a 16 bit shift* register.*** _______________________________________________________________* ___/ \___* shift_en* __________ _ _ _ _ _ _ _ __________ ......._ ______* shift_clk \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/** __ __ __ __ __ __ __ __ __ ...... _______* ___________/D0\/D1\/D2\/D3\/D4\/D5\/D6\/D7\________/D0\/ \/D7* shift_bit \__/\__/\__/\__/\__/\__/\__/\__/ \__/\....../\_______*******************************************************************************/module shift_register (bused_data, bd_ready, shift_bit, shift_en, shift_clk, reset); output [15:0] bused_data; // The bused output data output bd_ready; // The ready flag for the output input shift_bit; // The input shift bit input shift_en; // The shift enable input shift_clk; // The shift clock input reset; // The shift counter reset integer i; reg [15:0] bused_data; reg bd_ready; reg [3:0] count;parameter TRUE = 1'b1, FALSE = 1'b0;/******************************************************At each shift clock in which shift enable is true,clock in the shift bit into the shift register*******************************************************/always @ (posedge shift_clk)begin if (shift_en) begin bused_data[14:0] <= bused_data[15:1]; bused_data[15] <= shift_bit; endendalways @ (posedge shift_clk)begin if (reset) begin count <= 0; end else if (shift_en) begin {bd_ready, count} <= count + 1; endendendmodule //of shift_register</i></pre><hr size=5></BODY></HTML>⌨️ 快捷键说明
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