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<HTML><HEAD><TITLE>Some State Machine Examples...</TITLE></HEAD><BODY bgcolor = "#ffffc0" <CENTER><h1>Some State Machine Examples...</h1> <p><pre> <b> Using Synopsys comments, you can specify the state registers, andstates of your state machine. This is a generic state machine with fourstates. </b>// These are the symbolic names for statesparameter [1:0] //synopsys enum state_info S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3;// These are the current state and next state variablesreg [1:0] /* synopsys enum state_info */ state;reg [1:0] /* synopsys enum state_info */ next_state; // synopsys state_vector statealways @ (state or y or x)begin next_state = state; case (state) // synopsys full_case parallel_case S0: begin if (x) begin next_state = S1; end else begin next_state = S2; end end S1: begin if (y) begin next_state = S2; end else begin next_state = S0; end end S2: begin if (x & y) begin next_state = S3; end else begin next_state = S0; end end S3: begin next_state = S0; end endcaseendalways @ (posedge clk or posedge reset)begin if (reset) begin state <= S0; end else begin state <= next_state; endend <b> The same state machine can be one hot encoded by writing the following code. I do not recommend using FSM compiler if you code aone hot FSM directly. (You can also specify a one hot state machine when youevoke the FSM-Compiler, but you will have to note the values of thestate variables. To use FSM compiler you should code a state machinelike the example above. FSM compiler will add the extra flip-flops needed to make to FSM one hot) ... </b>// These are the symbolic names for statesparameter [1:0] S0 = 2'h0, S1 = 2'h1, S2 = 2'h2, S3 = 2'h3; parameter [3:0] //synopsys enum state_info s0 = 4'h1, s1 = 4'h2, s2 = 4'h4, s3 = 4'h8; // These are the current state and next state variablesreg [3:0] /* synopsys enum state_info */ state;reg [3:0] /* synopsys enum state_info */ next_state; // synopsys state_vector statealways @ (state or y or x)begin next_state = state; case (1) // synopsys full_case parallel_case state[S0]: begin if (x) begin next_state = 1 << S1; end else begin next_state = 1 << S2; end end state[S1]: begin if (y) begin next_state = 1 << S2; end else begin next_state = 1 << S0; end end state[S2]: begin if (x & y) begin next_state = 1 << S3; end else begin next_state = 1 << S0; end end state[S3]: begin next_state = 1 << S0; end endcaseendalways @ (posedge clk or posedge reset)begin if (reset) begin state <= 1 << S0; end else begin state <= next_state; endend<hr size=5></BODY></HTML>⌨️ 快捷键说明
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