appnote_zbtp.vhd

ZBT SRAM控制器参考设计

---------------------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: ctlr_p.vhd,v 1.1 1999-08-06 sanchez Exp $
--
---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
-- This ZBTSRAM controller assumes that only the read/write signal is being used
-- The other control signals are tied inside FPGA logic for future flexibility
-- The user can instead tie them on the board and save on the pins
---------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
package my_ctlr_p is
	component CTLR_P
	generic(ADDR_BITS : integer := 16;
		DATA_BITS : integer := 36);
	port(
	     dq		  : inout  std_logic_vector(DATA_BITS-1 downto 0);
	     addr	  : out    std_logic_vector(ADDR_BITS-1 downto 0);
	     lbo_n	  : out    std_logic;
	     clk	  : out    std_logic;
	     cke_n	  : out    std_logic;
	     ld_n	  : out    std_logic;
	     bwa_n	  : out    std_logic;
	     bwb_n	  : out    std_logic;
	     bwc_n	  : out    std_logic;
	     bwd_n	  : out    std_logic;
	     rw_n	  : out    std_logic;
	     oe_n	  : out    std_logic;
	     ce_n	  : out    std_logic;
	     ce2	  : out    std_logic;
	     ce2_n	  : out    std_logic;
	     zz		  : out    std_logic;
	     fpga_clk	  : out    std_logic;
	     ui_addr	  : in     std_logic_vector(ADDR_BITS-1 downto 0);
	     ui_write_data: in	   std_logic_vector(DATA_BITS-1 downto 0);
	     ui_rw_n	  : in     std_logic;
	     ui_rw_n_ctlr : in     std_logic;
	     ui_board_clk : in     std_logic;
	     ui_read_data : out    std_logic_vector(DATA_BITS-1 downto 0);
	     ui_clk_mirror_locked_int : out std_logic;
	     ui_clk_mirror_locked_ext : out std_logic;
	     ui_clk_mirror_fb         : in  std_logic);
	end component;
end my_ctlr_p;

library IEEE;
library unisim;
use unisim.vcomponents.all;
use IEEE.std_logic_1164.all;

entity CTLR_P is
	generic(ADDR_BITS : integer := 16;
		DATA_BITS : integer := 36);
	port(
	     dq		  : inout  std_logic_vector(DATA_BITS-1 downto 0);--bidirectional data bus to RAM
	     addr	  : out    std_logic_vector(ADDR_BITS-1 downto 0);--addr goes out to the RAM
	     lbo_n	  : out    std_logic;  --Burst Mode (0 = Linear, 1 = Interleaved)
	     clk	  : out    std_logic;  --2x clock goes to the RAM
	     cke_n	  : out    std_logic;  --Synchronous Clock Enable
	     ld_n	  : out    std_logic;  --Synchronous address Adv/LD
	     bwa_n	  : out    std_logic;  --Synchronous Byte Write Enable A
	     bwb_n	  : out    std_logic;  --Synchronous Byte Write Enable B
	     bwc_n	  : out    std_logic;  --Synchronous Byte Write Enable C
	     bwd_n	  : out    std_logic;  --Synchronous Byte Write Enable D
	     rw_n	  : out    std_logic;  --Read Write control goes out to the RAM
	     oe_n	  : out    std_logic;  --Output Enable
	     ce_n	  : out    std_logic;  --Synchronous Chip Enable
	     ce2	  : out    std_logic;  --Synchronous Chip Enable
	     ce2_n	  : out    std_logic;  --Synchronous Chip Enable
	     zz		  : out    std_logic;  --Snooze Mode
	     fpga_clk	  : out    std_logic;  --clk to use inside fpga (= ui_board_clk * 2)

	     ui_addr	  : in     std_logic_vector(ADDR_BITS-1 downto 0);--addr comes in from the user design
	     ui_write_data: in	   std_logic_vector(DATA_BITS-1 downto 0);--data comes in from the user design
	     ui_rw_n	  : in     std_logic;  --Read write control comes from the user design
	     ui_rw_n_ctlr : in     std_logic;  --Read write control comes from the user design
	     ui_board_clk : in     std_logic;  --incoming clock into the Virtex CLKDLL
	     ui_read_data : out    std_logic_vector(DATA_BITS-1 downto 0);--data read from SRAM
	     ui_clk_mirror_locked_int : out std_logic;
	     ui_clk_mirror_locked_ext : out std_logic;
	     ui_clk_mirror_fb         : in  std_logic); --2x clock feedback from the ui_board
end CTLR_P;

architecture RTL of CTLR_P is
signal write_data	: std_logic_vector(DATA_BITS-1 downto 0);
signal read_data	: std_logic_vector(DATA_BITS-1 downto 0);
signal rw_tff		: std_logic_vector(DATA_BITS-1 downto 0);
signal rw_n_p		: std_logic;
signal fpga_clk_a	: std_logic;

component DATABITS_INOUT
	port(
	     read_data 		: out   std_logic_vector(DATA_BITS-1 downto 0);
	     dq			: inout std_logic_vector(DATA_BITS-1 downto 0);
	     write_data		: in    std_logic_vector(DATA_BITS-1 downto 0);
	     rw_tff		: in    std_logic_vector(DATA_BITS-1 downto 0);
	     fpga_clk		: in    std_logic);
end component;
 
component PIPELINED_STAGES_P 
	port(
	     ui_read_data	: out   std_logic_vector(DATA_BITS-1 downto 0);
	     write_data		: out   std_logic_vector(DATA_BITS-1 downto 0);
	     rw_tff		: out   std_logic_vector(DATA_BITS-1 downto 0);
	     ui_write_data    	: in    std_logic_vector(DATA_BITS-1 downto 0);
 	     ui_rw_n		: in    std_logic;
	     read_data		: in    std_logic_vector(DATA_BITS-1 downto 0);
	     fpga_clk		: in    std_logic);
end component;

component ADDRBITS_OUT
	port(
	     addr	: out std_logic_vector(ADDR_BITS-1 downto 0);
	     ui_addr	: in  std_logic_vector(ADDR_BITS-1 downto 0);
	     fpga_clk	: in  std_logic);
end component;

component OBUF_F_16
	port(I : in std_logic; O : out std_logic);
end component;

component TIE_UNUSED_SIGS
	port(
	     lbo_n, cke_n, ld_n	: out std_logic;
	     bwa_n, bwb_n, bwc_n: out std_logic;
	     bwd_n, oe_n, ce_n	: out std_logic;
	     ce2, ce2_n, zz	: out std_logic);
end component; 

component DLL_2X_BOARD
	port(
	     clk2x_int			: out std_logic;
	     ui_clk_mirror_locked_int	: out   std_logic;
	     clk2x_ext			: out   std_logic;
	     ui_clk_mirror_locked_ext	: out   std_logic;
	     ui_board_clk		: in    std_logic;
	     ui_clk_mirror_fb		: in    std_logic);
end component;

begin

---------------------------------------------------------------------------------------
-- write data and read/write has to go thru two levels of pipelining for the 
-- Pipelined ZBT SRAM and one level for the Flowthru ZBT SRAM
-- This module provides appropriate number of pipeline stages
-- and fans out the read/write signal using a tree of FFs
---------------------------------------------------------------------------------------

I_pipelined_stages_p: PIPELINED_STAGES_P port map(
	     					  ui_read_data=>ui_read_data,
	     					  write_data=>write_data,
	    					  rw_tff=>rw_tff,
					  	  ui_write_data=>ui_write_data,
 	     					  ui_rw_n=>ui_rw_n_ctlr,
	     					  read_data=>read_data,
	     					  fpga_clk=>fpga_clk_a);

I_databits_inout: DATABITS_INOUT port map(
	     				  read_data=>read_data,
	     				  dq=>dq,
	     				  write_data=>write_data,
	     				  rw_tff=>rw_tff,
	     				  fpga_clk=>fpga_clk_a);

I_addrbits_out: ADDRBITS_OUT port map( 
	     			      addr=>addr,
	     			      ui_addr=>ui_addr,
	     			      fpga_clk=>fpga_clk_a);

---------------------------------------------------------------------------------------
-- The read/write control signal goes directly to the ZBT SRAM
---------------------------------------------------------------------------------------

	process(fpga_clk_a) begin
		if (fpga_clk_a 'event and fpga_clk_a = '1') then
			rw_n_p <= ui_rw_n;
		end if;
	end process;

I_obuf0: OBUF_F_16 port map(I=>rw_n_p, O=>rw_n);

I_tie_unused_sigs: TIE_UNUSED_SIGS port map(
	     				    lbo_n=>lbo_n, cke_n=>cke_n, ld_n=>ld_n,
	     				    bwa_n=>bwa_n, bwb_n=>bwb_n, bwc_n=>bwc_n,
	     				    bwd_n=>bwd_n, oe_n=>oe_n, ce_n=>ce_n,
	     				    ce2=>ce2, ce2_n=>ce2_n, zz=>zz);

I_dll_2x_board: DLL_2X_BOARD port map(
	     			      clk2x_int=>fpga_clk_a,
	     			      ui_clk_mirror_locked_int=>ui_clk_mirror_locked_int,
	     			      clk2x_ext=>clk,
	     			      ui_clk_mirror_locked_ext=>ui_clk_mirror_locked_ext,
	     			      ui_board_clk=>ui_board_clk,
				      ui_clk_mirror_fb=>ui_clk_mirror_fb);

fpga_clk <= fpga_clk_a;

end RTL;
----------------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: addrbits_out.vhd,v 1.1 1999-08-05 sanchez Exp $
--
----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
-- Module for interfacing address with the ZBTSRAM
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;

entity ADDRBITS_OUT is
	generic(ADDR_BITS :integer :=16);
	port(
-- Interfaces to user logic
	     ui_addr : in  std_logic_vector(ADDR_BITS-1 downto 0);
	     fpga_clk: in  std_logic;
-- Interface to ZBT SRAM
	     addr    : out std_logic_vector(ADDR_BITS-1 downto 0));
end ADDRBITS_OUT;

architecture RTL of ADDRBITS_OUT is
signal addr_p : std_logic_vector(ADDR_BITS-1 downto 0);

component OBUF_F_16
	port( I : in  std_logic;
	      O : out std_logic);
end component;

begin

	process(fpga_clk) begin
		if (fpga_clk 'event and fpga_clk = '1') then
			for i in 0 to ADDR_BITS-1 loop
				addr_p(i) <= ui_addr(i);
			end loop;
		end if;
	end process;

g0:	for i in 0 to ADDR_BITS-1 generate

	 obuf_addr: OBUF_F_16 port map(I=>addr_p(i), O=>addr(i));

	end generate;
	
end RTL;
---------------------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: databits_inout.vhd,v 1.1 1999-08-05 sanchez Exp $
--
---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
-- Module for interfacing data with the ZBTSRAM
---------------------------------------------------------------------------------------

library IEEE;
library unisim;
use unisim.vcomponents.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DATABITS_INOUT is 
	generic(DATA_BITS : integer := 36);
	port(
-- Interface to DATABITS_INOUT
	     read_data	: out   std_logic_vector(DATA_BITS-1 downto 0);
	     write_data	: in	std_logic_vector(DATA_BITS-1 downto 0);
	     rw_tff	: in 	std_logic_vector(DATA_BITS-1 downto 0);
	     fpga_clk	: in 	std_logic;
-- Interface to ZBT SRAM
	     dq		: inout std_logic_vector(DATA_BITS-1 downto 0));
end DATABITS_INOUT;

architecture RTL of DATABITS_INOUT is
signal write_data_p : std_logic_vector(DATA_BITS-1 downto 0);
signal rw_tff_p     : std_logic_vector(DATA_BITS-1 downto 0);

component IOBUF_F_16
	port(O : out  	std_logic;