appnote_zbtf.vhd

ZBT SRAM控制器参考设计

	     rw_tff	: in 	std_logic_vector(DATA_BITS-1 downto 0);
	     fpga_clk	: in 	std_logic;
-- Interface to ZBT SRAM
	     dq		: inout std_logic_vector(DATA_BITS-1 downto 0));
end DATABITS_INOUT;

architecture RTL of DATABITS_INOUT is
signal write_data_p : std_logic_vector(DATA_BITS-1 downto 0);
signal rw_tff_p     : std_logic_vector(DATA_BITS-1 downto 0);

component IOBUF_F_16
	port(O : out  	std_logic;
	     IO: inout 	std_logic;
	     I : in 	std_logic;
	     T : in  	std_logic);
end component;

begin

	process(fpga_clk)
	begin
		if (fpga_clk 'event and fpga_clk = '1') then
		    for i in 0 to DATA_BITS-1 loop
		      write_data_p(i) <= write_data(i);
		      rw_tff_p(i)     <= rw_tff(i);
                    end loop;
		end if;
       end process;

g0:	for i in 0 to DATA_BITS-1 generate

		iobuf:   IOBUF_F_16 port map(O=>read_data(i),IO=>dq(i),I=>write_data_p(i),T=>rw_tff_p(i));

        end generate;
end RTL;
--------------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTIBILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: tie_unused_sigs.vhd,v 1.1 1999-08-05 sanchez Exp $
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
--Module for tying the unused control signals
--------------------------------------------------------------------------------

library IEEE;
library unisim;
use unisim.vcomponents.all;
use IEEE.std_logic_1164.all;

--------------------------------------------------------------------------------
-- Interface to ZBT SRAM
--------------------------------------------------------------------------------

entity TIE_UNUSED_SIGS is
	port(
	     lbo_n	: out std_logic; --Burst Mode (0=Linear, 1=Interleaved)
	     cke_n	: out std_logic; --Synchronous Clock Enable
	     ld_n	: out std_logic; --Synchronous address Adv/LD
	     bwa_n	: out std_logic; --Synchronous Byte Write Enable A
	     bwb_n	: out std_logic; --Synchronous Byte Write Enable B
	     bwc_n	: out std_logic; --Synchronous Byte Write Enable C
	     bwd_n	: out std_logic; --Synchronous Byte Write Enable D
	     oe_n	: out std_logic; --OUt Enable
	     ce_n	: out std_logic; --Synchronous Chip Enable
	     ce2	: out std_logic; --Synchronous Chip Enable
	     ce2_n	: out std_logic; --Synchronous Chip Enable
	     zz		: out std_logic);--Snooze Mode
end TIE_UNUSED_SIGS;

architecture RTL of TIE_UNUSED_SIGS is
signal lbo_n_w	: std_logic;
signal cke_n_w	: std_logic;
signal ld_n_w	: std_logic;
signal bwa_n_w	: std_logic;
signal bwb_n_w	: std_logic;
signal bwc_n_w	: std_logic;
signal bwd_n_w	: std_logic;
signal oe_n_w	: std_logic;
signal ce_n_w	: std_logic;
signal ce2_w	: std_logic;
signal ce2_n_w	: std_logic;
signal zz_w	: std_logic;

component OBUF
	port(I : in std_logic; O : out std_logic);
end component;

begin

lbo_n_w	<= '0';
cke_n_w	<= '0';
ld_n_w	<= '0';
bwa_n_w	<= '0';
bwb_n_w	<= '0';
bwc_n_w	<= '0';
bwd_n_w	<= '0';
oe_n_w	<= '0';
ce_n_w	<= '0';
ce2_w	<= '1';
ce2_n_w	<= '0';
zz_w	<= '0';

I_obuf_lbo_n: OBUF port map(I=>lbo_n_w, O=>lbo_n);
I_obuf_cke_n: OBUF port map(I=>cke_n_w, O=>cke_n);
I_obuf_ld_n:  OBUF port map(I=>ld_n_w, O=>ld_n);
I_obuf_bwa_n: OBUF port map(I=>bwa_n_w, O=>bwa_n);
I_obuf_bwb_n: OBUF port map(I=>bwb_n_w, O=>bwb_n);
I_obuf_bwc_n: OBUF port map(I=>bwc_n_w, O=>bwc_n);
I_obuf_bwd_n: OBUF port map(I=>bwd_n_w, O=>bwd_n);
I_obuf_oe_n:  OBUF port map(I=>oe_n_w, O=>oe_n);
I_obuf_ce_n:  OBUF port map(I=>ce_n_w, O=>ce_n);
I_obuf_ce2:   OBUF port map(I=>ce2_w, O=>ce2);
I_obuf_ce2_n: OBUF port map(I=>ce2_n_w, O=>ce2_n);
I_obuf_zz:    OBUF port map(I=>zz_w, O=>zz);

end RTL;
------------------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: pipelined_stages_zbtf.vhd,v 1.1 1999-08-04 sanchez Exp $
--
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
-- Customize the Controller for the ZBT SRAM for the Flowthru variety
------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity PIPELINED_STAGES_F is
	generic(DATA_BITS	: integer := 36);
	port(
	     ui_write_data	: in  std_logic_vector(DATA_BITS-1 downto 0);
	     ui_rw_n		: in  std_logic;
	     ui_read_data	: out std_logic_vector(DATA_BITS-1 downto 0);
	     write_data		: out std_logic_vector(DATA_BITS-1 downto 0);
	     read_data		: in  std_logic_vector(DATA_BITS-1 downto 0);
	     rw_tff		: out std_logic_vector(DATA_BITS-1 downto 0);
	     fpga_clk		: in  std_logic);
end PIPELINED_STAGES_F;

architecture RTL of PIPELINED_STAGES_F is
signal rw_p1		: std_logic_vector(3 downto 0);
signal rw_p2		: std_logic_vector(3 downto 0);

begin

	process (fpga_clk)
	begin
		if (fpga_clk 'event and fpga_clk = '1') then

	-- a tree of FFs to reduce fanout and add one pipelining stage
			for i in 0 to 3 loop
				rw_p1(i)    <= ui_rw_n;
				rw_p2(i)    <= rw_p1(i);
			end loop;

	-- add one pipeline stage to data being written to the ZBT SRAM
			for i in 0 to DATA_BITS-1 loop
				rw_tff(i)        <= ui_rw_n;
				write_data(i) <= ui_write_data(i);
			end loop;

	-- register the data being read back from the ZBT SRAM
			if (rw_p2(0) = '1') then 	
				for i in 0 to 8 loop
					ui_read_data(i) <= read_data(i);
				end loop;
			end if;
			if (rw_p2(1) = '1') then 	
				for i in 9 to 17 loop
					ui_read_data(i) <= read_data(i);
				end loop;
			end if;
			if (rw_p2(2) = '1') then 	
				for i in 18 to 26 loop
					ui_read_data(i) <= read_data(i);
				end loop;
			end if;
			if (rw_p2(3) = '1') then 	
				for i in 27 to 35 loop
					ui_read_data(i) <= read_data(i);
				end loop;
			end if;
								
		end if;
	end process;
end RTL;
-----------------------------------------------------------------------------
--
--	Author :	Sergio Sanchez
--	Email  :	[e-mail]
--	Phone  :	[phone]
--	Company:	Xilinx
--
--   Disclaimer:	THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--			WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--			IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--			A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--			Copyright (c) 1999 Xilinx, Inc.
--			All rights reserved
--
--	Version:	$Id: dll_2x_board.vhd,v 1.1 1999-08-05 sanchez Exp $
--
-----------------------------------------------------------------------------

-----------------------------------------------------------------------------
--This module instantiates two DLLs for generating de-skewed 2X clocks
--one for use inside the fpga (_int)
--and one for interfacing with other components on the Board (_ext)
-----------------------------------------------------------------------------

library IEEE;
library unisim;
use unisim.vcomponents.all;
use IEEE.std_logic_1164.all;

entity DLL_2X_BOARD is 
	port(
	     ui_board_clk		: in  std_logic; --Incoming clock
	     ui_clk_mirror_fb		: in  std_logic; --Feedback signal for the external clock
							 --user has to provide connection on the board
	     clk2x_int			: out std_logic; --2X clk available inside the fpga
	     ui_clk_mirror_locked_int	: out std_logic; --locked signal for the internal clock
	     clk2x_ext			: out std_logic; --2X clk going out of the fpga
	     ui_clk_mirror_locked_ext	: out std_logic);--locked signal for the external clock
end DLL_2X_BOARD;

architecture RTL of DLL_2X_BOARD is
signal logic0			: std_logic;
signal clkin			: std_logic;
signal clk_mirror_fb_ext	: std_logic;
signal clk2xdll_int		: std_logic;
signal clk2xdll_ext		: std_logic;
signal clk_mirror_locked_ext	: std_logic;
signal clk_mirror_locked_ext_inv: std_logic;
signal clk_mirror_locked_int	: std_logic;
signal clk_mirror_locked_int_inv: std_logic;
signal clk2x_inta		: std_logic;

component IBUFG
	port(I : in std_logic; O : out std_logic);
end component;

component CLKDLL
	port(clkin : in std_logic;
	     clkfb : in std_logic;
	     rst   : in std_logic;
	     locked: out std_logic;
	     clk2x : out std_logic);
end component;

component BUFG
	port(I : in std_logic; O : out std_logic);
end component;

component OBUF_F_16 
	port(I : in std_logic; O : out std_logic);
end component;

component OBUF_F_8
	port(I : in std_logic; O : out std_logic);
end component;

begin

logic0 <= '0'; -- Never reset the DLL

I_ibufg_clkin: IBUFG port map(I=>ui_board_clk, O=>clkin);

I_clkdll_int : CLKDLL port map(clkin=>clkin, clkfb=>clk2x_inta, rst=>logic0, clk2x=>clk2xdll_int, locked=>clk_mirror_locked_int);

I_bufg_clk2x_int: BUFG port map(I=>clk2xdll_int, O=>clk2x_inta);

clk2x_int <= clk2x_inta;

I_clkdll_ext : CLKDLL port map(clkin=>clkin, clkfb=>clk_mirror_fb_ext, rst=>logic0, clk2x=>clk2xdll_ext, locked=>clk_mirror_locked_ext);

clk_mirror_locked_int_inv <= not clk_mirror_locked_int;

I_obuf_clk_mirror_locked_int: OBUF_F_16 port map(I=>clk_mirror_locked_int_inv, O=>ui_clk_mirror_locked_int);

I_obuf_clk2x_ext: OBUF_F_8 port map(I=>clk2xdll_ext, O=>clk2x_ext);

I_ibufg_clk_mirror_fb_ext: IBUFG port map(I=>ui_clk_mirror_fb, O=>clk_mirror_fb_ext);

clk_mirror_locked_ext_inv <= not clk_mirror_locked_ext;

I_obuf_clk_mirror_locked_ext: OBUF_F_16 port map(I=>clk_mirror_locked_ext_inv, O=>ui_clk_mirror_locked_ext);

end RTL;