loadpw.v

来自「直接频率合成」· Verilog 代码 · 共 83 行

/*******************************************************************************
****************************************************************************
 **                                                                             
 **                                                                             
 ** Project Name         : DDS                                            
 **                                                                             
 ** Author               : Daniel J. Morelli
 ** Creation Date        : 03/03/96 22:15:42                                              
 ** Version Number       : 1.0                                                 
 **                                                                             
 ** Revision History     :                                                      
 **                                                                             
 ** Date          Initials         Modification                                 
 **                                                                             
 **                                                                             
 ** Description          :                                                      
 **                                                                             
 ** This module will register the phase word and output a synchronous phase
 ** word to the phase modulator
 ** 
 **                                                                             
 *******************************************************************************/

 module loadpw(
	RESETN,				// global reset
	SYSCLK,				// system clock
	PHASEWORD,			// input phase word from external pins
	PWWRN,				// low asserted frequency word write strobe
	SYNCPHSWD);			// synchronous phase word

// Port types

input SYSCLK, RESETN, PWWRN;
input[7:0] PHASEWORD;

output[7:0] SYNCPHSWD;

reg[7:0] pwreg;				// input phase word registered
reg pwwrnm;				// meta-stable phase word write strobe
reg pwwrns;				// synchronous phase word write strobe
reg load;				// synchronous load strobes
reg[7:0] phswd;		// PW registered values

// design architecture
	assign SYNCPHSWD = phswd;

	// register the input phase word
	always@(posedge PWWRN or negedge RESETN)
	if (!RESETN)
		pwreg <= 8'h00;
	else
		pwreg <= PHASEWORD;

	// get a synchronous load strobe on the rising edge of PWWRN
	always@(posedge SYSCLK or negedge RESETN)
	if (!RESETN)
	begin
		pwwrnm <= 1;
		pwwrns <= 1;
		load <= 0;
	end
	else
	begin
		pwwrnm <= PWWRN;
		pwwrns <= pwwrnm;			// got a synchronous PWWRN
		if ((!pwwrns)&(pwwrnm))
			load <= 1;				// got rising edge
		else
			load <= 0;
	end

	// register the phase word
	always@(posedge SYSCLK or negedge RESETN)
	if (!RESETN)
		phswd <= 8'h00;
	else
		if (load)
			phswd <= pwreg;
		else
			phswd <= phswd;

endmodule