📄 test2.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/144( 12%) 27/ 72( 37%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 1/144( 0%) 24/ 72( 33%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 3/144( 2%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 1/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 45 sysclk
DFF 18 |BFENPIN:6|:6
LCELL 10 |PHYUZ:13|:402
DFF 4 |HZ100:3|:2
DFF 4 :4
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** EQUATIONS **
bfre : INPUT;
clr : INPUT;
keypha : INPUT;
keyphb : INPUT;
sysclk : INPUT;
-- Node name is ':18' = 'bclr'
-- Equation name is 'bclr', location is LC7_A15, type is buried.
bclr = DFFE( _EQ001, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ001 = !_LC3_A15 & _LC5_A15
# _LC1_B4
# clr_clr;
-- Node name is ':9' = 'clr_clr'
-- Equation name is 'clr_clr', location is LC1_B12, type is buried.
clr_clr = DFFE( clr, _LC3_D13, VCC, VCC, VCC);
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _EC2_A;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _EC12_A;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _EC4_A;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _EC11_A;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _EC1_A;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _EC10_A;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _EC3_A;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _EC9_A;
-- Node name is '|ACHANLE:7|:29' = '|ACHANLE:7|acc0'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = DFFE( _EQ002, _LC1_B10, VCC, VCC, VCC);
_EQ002 = !bclr & !_LC1_A7;
-- Node name is '|ACHANLE:7|:28' = '|ACHANLE:7|acc1'
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = DFFE( _EQ003, _LC1_B10, VCC, VCC, VCC);
_EQ003 = _LC1_A7 & !_LC2_A16 & !_LC6_A7
# !_LC1_A7 & !_LC2_A16 & _LC6_A7;
-- Node name is '|ACHANLE:7|:27' = '|ACHANLE:7|acc2'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = DFFE( _EQ004, _LC1_B10, VCC, VCC, VCC);
_EQ004 = !_LC1_A7 & !_LC2_A16 & _LC4_A7
# !_LC2_A16 & _LC4_A7 & !_LC6_A7
# _LC1_A7 & !_LC2_A16 & !_LC4_A7 & _LC6_A7;
-- Node name is '|ACHANLE:7|:26' = '|ACHANLE:7|acc3'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = DFFE( _EQ005, _LC1_B10, VCC, VCC, VCC);
_EQ005 = _LC2_A9 & !_LC2_A16 & !_LC5_A7
# !_LC2_A9 & !_LC2_A16 & _LC5_A7;
-- Node name is '|ACHANLE:7|:25' = '|ACHANLE:7|acc4'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ006, _LC1_B10, VCC, VCC, VCC);
_EQ006 = _LC1_A1 & !_LC2_A9 & !_LC2_A16
# _LC1_A1 & !_LC2_A16 & !_LC5_A7
# !_LC1_A1 & _LC2_A9 & !_LC2_A16 & _LC5_A7;
-- Node name is '|ACHANLE:7|:24' = '|ACHANLE:7|acc5'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = DFFE( _EQ007, _LC1_B10, VCC, VCC, VCC);
_EQ007 = !_LC1_A1 & !_LC2_A16 & _LC8_A6
# !_LC1_A19 & !_LC2_A16 & _LC8_A6
# _LC1_A1 & _LC1_A19 & !_LC2_A16 & !_LC8_A6;
-- Node name is '|ACHANLE:7|:23' = '|ACHANLE:7|acc6'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = DFFE( _EQ008, _LC1_B10, VCC, VCC, VCC);
_EQ008 = _LC1_A12 & !_LC2_A16 & !_LC8_A6
# _LC1_A12 & !_LC2_A10 & !_LC2_A16
# !_LC1_A12 & _LC2_A10 & !_LC2_A16 & _LC8_A6;
-- Node name is '|ACHANLE:7|:22' = '|ACHANLE:7|acc7'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ009, _LC1_B10, VCC, VCC, VCC);
_EQ009 = _LC1_A16 & !_LC2_A16 & !_LC6_A16
# !_LC1_A16 & !_LC2_A16 & _LC6_A16;
-- Node name is '|ACHANLE:7|:21' = '|ACHANLE:7|acc8'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = DFFE( _EQ010, _LC1_B10, VCC, VCC, VCC);
_EQ010 = !_LC1_A16 & !_LC2_A16 & _LC7_A16
# !_LC2_A16 & !_LC6_A16 & _LC7_A16
# _LC1_A16 & !_LC2_A16 & _LC6_A16 & !_LC7_A16;
-- Node name is '|ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A7', type is buried
!_LC5_A7 = _LC5_A7~NOT;
_LC5_A7~NOT = LCELL( _EQ011);
_EQ011 = !_LC4_A7
# !_LC1_A7
# !_LC6_A7;
-- Node name is '|ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ012);
_EQ012 = _LC2_A9 & _LC5_A7;
-- Node name is '|ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ013);
_EQ013 = _LC1_A1 & _LC2_A9 & _LC5_A7;
-- Node name is '|ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ014);
_EQ014 = _LC1_A12 & _LC2_A10 & _LC8_A6;
-- Node name is '|ACHANLE:7|:3'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = DFFE( _LC7_A16, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:5'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = DFFE( _LC1_A16, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:7'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = DFFE( _LC1_A12, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:9'
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = DFFE( _LC8_A6, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:11'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _LC1_A1, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:13'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = DFFE( _LC2_A9, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:15'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _LC4_A7, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:17'
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = DFFE( _LC6_A7, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|:19'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = DFFE( _LC1_A7, _LC1_B10, VCC, VCC, VCC);
-- Node name is '|ACHANLE:7|~71~1'
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