📄 mcu.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mcu is
port(clkf,clkp:in std_logic;
dd:in std_logic_vector(7 downto 0);
clr_in2:out std_logic;
qqp:out std_logic_vector(7 downto 0);
qqf:out std_logic_vector(3 downto 0));
end mcu;
architecture behav of mcu is
begin
clr_in2<=clkf or clkp;
process(clkp)
begin
if(clkp'event and clkp='1')then
qqp<=dd;
end if;
end process;
process(clkf)
begin
if(clkf'event and clkf='1')then
qqf<=dd(3 downto 0);
end if;
end process;
end behav;
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