📄 mcu.rpt
字号:
- 4 - C 05 OR2 2 0 1 0 :196
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mydesign\altera\maxplus\lishanew\lisha\mcu.rpt
mcu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/144( 2%) 1/ 72( 1%) 1/ 72( 1%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 3/144( 2%) 1/ 72( 1%) 0/ 72( 0%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydesign\altera\maxplus\lishanew\lisha\mcu.rpt
mcu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clkp
INPUT 5 clkf
Device-Specific Information: e:\mydesign\altera\maxplus\lishanew\lisha\mcu.rpt
mcu
** EQUATIONS **
clkf : INPUT;
clkp : INPUT;
dd0 : INPUT;
dd1 : INPUT;
dd2 : INPUT;
dd3 : INPUT;
dd4 : INPUT;
dd5 : INPUT;
dd6 : INPUT;
dd7 : INPUT;
-- Node name is 'clr_in2'
-- Equation name is 'clr_in2', type is output
clr_in2 = _LC4_C5;
-- Node name is 'qqf0'
-- Equation name is 'qqf0', type is output
qqf0 = _LC7_A19;
-- Node name is 'qqf1'
-- Equation name is 'qqf1', type is output
qqf1 = _LC1_B4;
-- Node name is 'qqf2'
-- Equation name is 'qqf2', type is output
qqf2 = _LC3_B1;
-- Node name is 'qqf3'
-- Equation name is 'qqf3', type is output
qqf3 = _LC2_A19;
-- Node name is 'qqp0'
-- Equation name is 'qqp0', type is output
qqp0 = _LC1_A19;
-- Node name is 'qqp1'
-- Equation name is 'qqp1', type is output
qqp1 = _LC2_B1;
-- Node name is 'qqp2'
-- Equation name is 'qqp2', type is output
qqp2 = _LC1_B1;
-- Node name is 'qqp3'
-- Equation name is 'qqp3', type is output
qqp3 = _LC7_A20;
-- Node name is 'qqp4'
-- Equation name is 'qqp4', type is output
qqp4 = _LC5_A2;
-- Node name is 'qqp5'
-- Equation name is 'qqp5', type is output
qqp5 = _LC1_B21;
-- Node name is 'qqp6'
-- Equation name is 'qqp6', type is output
qqp6 = _LC6_B3;
-- Node name is 'qqp7'
-- Equation name is 'qqp7', type is output
qqp7 = _LC1_A2;
-- Node name is ':12'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( dd7, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':14'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( dd6, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':16'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = DFFE( dd5, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':18'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = DFFE( dd4, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':20'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = DFFE( dd3, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':22'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( dd2, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':24'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( dd1, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':26'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( dd0, GLOBAL( clkp), VCC, VCC, VCC);
-- Node name is ':28'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = DFFE( dd3, GLOBAL( clkf), VCC, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( dd2, GLOBAL( clkf), VCC, VCC, VCC);
-- Node name is ':32'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = DFFE( dd1, GLOBAL( clkf), VCC, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = DFFE( dd0, GLOBAL( clkf), VCC, VCC, VCC);
-- Node name is ':196'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ001);
_EQ001 = clkp
# clkf;
Project Information e:\mydesign\altera\maxplus\lishanew\lisha\mcu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,593K
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