tap_test.v

verilog 实现的jtag ip模块 包括了测试程序

`include "tap_top.v"
module tap_test;
reg tms,tck,trst,tdi,debug_tdi,bs_tdi,mbist_tdi;
wire tdo_pad,tdo_padoe,shift_dr,pause_dr,update_dr,capture_dr,extest_select;
wire sample_preload_select,mbist_select,debug_select,tdo;
reg[3:0]inst_code;
parameter dely=100;
integer i;
tap_top tap1(
                // JTAG pads
                tms, 
                tck, 
                trst, 
                tdi, 
                tdo_pad, 
                tdo_padoe,

                // TAP states
                shift_dr,
                pause_dr, 
                update_dr,
                capture_dr,
                
                // Select signals for boundary scan or mbist
                extest_select, 
                sample_preload_select,
                mbist_select,
                debug_select,
                
                // TDO signal that is connected to TDI of sub-modules.
                tdo, 
                
                // TDI signals from sub-modules
                debug_tdi,    // from debug module
                bs_tdi, // from Boundary Scan Chain
                mbist_tdi     // from Mbist Chain
              );
              
always #(dely/2) tck=~tck;
initial begin
//IDCODE_TEST
inst_code=`IDCODE;
tck=0;trst=1;//Test logic Reset;     
#dely trst=0;tms=0;//Run test/idle
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=1;//Select-DR-Scan
#dely tms=0;//capture-DR
#dely tms=0;//Shift-DR
for(i=31;i>0;i=i-1)
#dely tms=0;
#dely tms=1;//Exit1-DR
#dely tms=1;//Update-DR
#dely tms=0;//Run-test/idle
//IDCODE_TEST_END
//BYPASS_TEST
inst_code=`BYPASS;
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=1;//Select-DR-Scan
#dely tms=0;//capture-DR
#dely tdi=0;//shift-DR
for(i=5;i>0;i=i-1)//test signal generator
begin
#dely tdi=~tdi;tms=0;
end
#dely tms=1;//Exit1-DR
#dely tms=1;//Update-DR
#dely tms=0;//Run-test/idle
//BYPASS_TEST_END
//EXTEST_TEST
inst_code=`EXTEST;
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=0;bs_tdi=1'b0;//Run-test/idle
for(i=16;i>0;i=i-1)//test signal generator
begin
#(dely/8) bs_tdi=~bs_tdi;
end
//EXTEST_TEST_END
//DEBUG_TEST
inst_code=`DEBUG;
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=0;debug_tdi=1'b0;//Run-test/idle
for(i=16;i>0;i=i-1)//test signal generator
begin
#(dely/8) debug_tdi=~debug_tdi;
end
//DEBUG_TEST_END
//MBIST_TEST
inst_code=`MBIST;
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=0;mbist_tdi=1'b0;//Run-test/idle
for(i=16;i>0;i=i-1)//test signal generator
begin
#(dely/8) mbist_tdi=~mbist_tdi;
end
//MBIST_TEST_END
//SAMPLE_PRELOAD_TEST
inst_code=`SAMPLE_PRELOAD;
#dely tms=1;//select-DR-scan
#dely tms=1;//select-IR-Scan
#dely tms=0;//capture-IR
#dely tms=0;//shift-IR
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];inst_code[3:0]={1'b0,inst_code[3:1]};tms=0;
#dely tdi=inst_code[0];tms=1;//Exit1-IR
#dely tms=1;//Update_IR
#dely tms=0;bs_tdi=1'b0;//Run-test/idle
for(i=16;i>0;i=i-1)//test signal generator
begin
#(dely/8) bs_tdi=~bs_tdi;
end
//SAMPLE_PRELOAD_TEST_END
#(dely*5) $finish;     
end    
endmodule