新建 文本文档.txt

ask调制

library ieee; 
use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 entity PL_ASK2 is 
port(clk            :in std_logic;                  
 start        :in std_logic;                   
x            :in std_logic;                   
 y            :out std_logic);       
end PL_ASK2; 
architecture behav of PL_ASK2 is
signal q:integer range 0 to 11;  
signal xx:std_logic;                                
signal m:integer range 0 to 5;
               
 begin process(clk) 
                                           
begin if clk’event and clk=’1’ 
then xx<=x;      
     if start=’0’ then q<=0;                         
 elsif q=11 then q<=0;       
else q<=q+1;      
 end if; 
end if; 
end process; 
process(xx,q)                                        
begin   if q=11 then m<=0; 
                        elsif q=10 then  
                               if m<=3 then y<=’0’;  
                     else y<=’1’;   
    end if; 
elsif    xx’event and xx=’1’then m<=m+1;
end if;
 end process;
 end behav;      


文件名：PL_ASK 功能：基于 VHDL 硬件描述语言，对基带信号进行 ASK 振幅调制


library ieee;
 use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
 entity PL_ASK is port
(clk          :in std_logic;                      ? ?系统时钟   
        start      :in std_logic;                      ? ?开始调制信号      
     x          :in std_logic;                      ? ?基带信号   
        y          :out std_logic);                  ? ?调制信号
 end PL_ASK; 
architecture behav of PL_ASK is 
signal q:integer range 0 to 3;                  ? ?分频计数器 
signal f :std_logic;                                  ? ?载波信号 
begin process(clk) 
begin if clk’event and clk=’1’ 
then         if start=’0’ then q<=0;    
   elsif q<=1 then f<=’1’;q<=q+1; ? ?改变 q 后面数字的大小，就可以改变载波信号的占空比   
    elsif q=3 then f<=’0’;q<=0;        ? ?改变 q 后面数字的大小，就可以改变载波信号的频率 
     else    f<=’0’;q<=q+1;      
 end if; 
end if;
 end process; 
y<=x and f;   
                                   ? ?对基带码进行调制 end behav;