cpu.vhd

ALTERA NIOS处理器实验

                signal pc :  STD_LOGIC_VECTOR (20 DOWNTO 0);

begin

  the_CPU_address_request : CPU_address_request
    port map(
      ic_flush => internal_ic_flush2,
      p1_flush => internal_p1_flush,
      pc => pc,
      clk => clk,
      d1_instruction_fifo_read_data_bad => d1_instruction_fifo_read_data_bad,
      do_branch => do_branch,
      do_jump => do_jump,
      ic_read => ic_read,
      ic_wait => ic_wait,
      instruction_fifo_read_data_bad => instruction_fifo_read_data_bad,
      pipe_run => pipe_run,
      reset_n => reset_n,
      target_address => internal_target_address
    );


  the_CPU_target_address : CPU_target_address
    port map(
      target_address => internal_target_address,
      branch_base => branch_base,
      clk => clk,
      do_branch => do_branch,
      do_jump => do_jump,
      jump_target_address => jump_target_address,
      pipe_run => pipe_run,
      reset_n => reset_n,
      signed_branch_offset => signed_branch_offset
    );


  ic_address <= pc & A_ToStdLogicVector('0');
  --vhdl renameroo for output signals
  ic_flush <= internal_ic_flush2;
  --vhdl renameroo for output signals
  p1_flush <= internal_p1_flush;
  --vhdl renameroo for output signals
  target_address <= internal_target_address;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_cpu_instruction_fifo_fifo_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal fifo_read : IN STD_LOGIC;
                 signal fifo_wr_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal fifo_write : IN STD_LOGIC;
                 signal flush : IN STD_LOGIC;
                 signal ic_wait : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal fifo_rd_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal fifo_read_data_bad : OUT STD_LOGIC;
                 signal ic_read : OUT STD_LOGIC
              );
end entity CPU_cpu_instruction_fifo_fifo_module;


architecture europa of CPU_cpu_instruction_fifo_fifo_module is
                signal bad_news :  STD_LOGIC;
                signal continue_read_cycle :  STD_LOGIC;
                signal dont_forget_to_reset_ic_read :  STD_LOGIC;
                signal fifo_becoming_empty :  STD_LOGIC;
                signal fifo_dec :  STD_LOGIC;
                signal fifo_inc :  STD_LOGIC;
                signal fifo_reg_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal fifo_reg_0_read_select :  STD_LOGIC;
                signal fifo_reg_0_write_select :  STD_LOGIC;
                signal fifo_reg_1 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal fifo_reg_1_read_select :  STD_LOGIC;
                signal fifo_reg_1_write_select :  STD_LOGIC;
                signal fifo_reg_2 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal fifo_reg_2_read_select :  STD_LOGIC;
                signal fifo_reg_2_write_select :  STD_LOGIC;
                signal ic_read_confusion :  STD_LOGIC;
                signal ic_read_prime :  STD_LOGIC;
                signal internal_fifo_empty :  STD_LOGIC;
                signal internal_fifo_rd_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_fifo_read_data_bad :  STD_LOGIC;
                signal internal_ic_read3 :  STD_LOGIC;
                signal next_read_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal read_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal reset_ic_read :  STD_LOGIC;
                signal set_ic_read :  STD_LOGIC;
                signal unxshiftxread_pointerxxrdaddress_calculatorx0_in :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal unxshiftxread_pointerxxrdaddress_calculatorx0_out :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal unxshiftxwrite_pointerxxwraddress_calculatorx1_in :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal unxshiftxwrite_pointerxxwraddress_calculatorx1_out :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal write_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_fifo_empty <= '1';
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        if std_logic'(fifo_becoming_empty) = '1' then 
          internal_fifo_empty <= '1';
        elsif std_logic'((fifo_write AND NOT fifo_read)) = '1' then 
          internal_fifo_empty <= '0';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_ic_read3 <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(NOT ic_wait) = '1' then 
        if std_logic'(reset_ic_read) = '1' then 
          internal_ic_read3 <= '0';
        elsif std_logic'(set_ic_read) = '1' then 
          internal_ic_read3 <= '1';
        end if;
      end if;
    end if;

  end process;

  set_ic_read <= fifo_becoming_empty OR internal_fifo_empty;
  reset_ic_read <= ((fifo_write AND NOT fifo_read)) OR ((dont_forget_to_reset_ic_read AND NOT internal_fifo_empty));
  ic_read_confusion <= set_ic_read AND reset_ic_read;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dont_forget_to_reset_ic_read <= '1';
    elsif clk'event and clk = '1' then
      if true then 
        if std_logic'((((dont_forget_to_reset_ic_read AND NOT ic_wait)) OR ((internal_fifo_empty AND dont_forget_to_reset_ic_read)))) = '1' then 
          dont_forget_to_reset_ic_read <= '0';
        elsif std_logic'((((fifo_write AND NOT fifo_read)) AND ic_wait)) = '1' then 
          dont_forget_to_reset_ic_read <= '1';
        end if;
      end if;
    end if;

  end process;

  fifo_inc <= fifo_write;
  fifo_dec <= fifo_read AND NOT (internal_fifo_read_data_bad);
  next_read_pointer <= Std_Logic_Vector'(read_pointer(1 DOWNTO 0) & A_ToStdLogicVector(read_pointer(2)));
  fifo_becoming_empty <= ((to_std_logic(((next_read_pointer = write_pointer))) AND ((fifo_read AND NOT fifo_write)))) OR flush;
  ic_read_prime <= internal_fifo_empty OR continue_read_cycle;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      continue_read_cycle <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        if std_logic'(NOT ic_wait) = '1' then 
          continue_read_cycle <= '0';
        elsif std_logic'(ic_read_prime) = '1' then 
          continue_read_cycle <= '1';
        end if;
      end if;
    end if;

  end process;

  internal_fifo_read_data_bad <= ((internal_fifo_empty AND NOT (fifo_write))) OR flush;
  bad_news <= ic_read_prime XOR internal_ic_read3;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_0 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if std_logic'((fifo_reg_0_write_select AND fifo_write)) = '1' then 
        fifo_reg_0 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_0_write_select <= write_pointer(0);
  fifo_reg_0_read_select <= read_pointer(0);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_1 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if std_logic'((fifo_reg_1_write_select AND fifo_write)) = '1' then 
        fifo_reg_1 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_1_write_select <= write_pointer(1);
  fifo_reg_1_read_select <= read_pointer(1);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_2 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if std_logic'((fifo_reg_2_write_select AND fifo_write)) = '1' then 
        fifo_reg_2 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_2_write_select <= write_pointer(2);
  fifo_reg_2_read_select <= read_pointer(2);