📄 at9802.h
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// Below define the bit field of read register.
//0x00,0x01(R)
typedef struct{ //General Purpose Input port
unsigned char dtr:1; //DTR
unsigned char rts:1; //RTS
unsigned char ll:1; //LL
unsigned char rl:1; //RL
unsigned char set:4; //
}V35_STS;
typedef union
{
unsigned char byte;
V35_STS bit;
}un_V35_STS;
//0x02(R)
#define PDST_R_P1_MATCH_127 1
#define PDST_R_P1_UNMATCH_127 0
#define PDST_R_P2_MATCH_127 1
#define PDST_R_P2_UNMATCH_127 0
#define PDST_R_P1_MATCH_ALLONE 1
#define PDST_R_P1_UNMATCH_ALLONE 0
#define PDST_R_P2_MATCH_ALLONE 1
#define PDST_R_P2_UNMATCH_ALLONE 0
typedef struct{ // Pattern Detector Register.
unsigned char port1_127:1; //Port 1 match RANDOM127.
unsigned char port2_127:1; //Port 2 match RANDOM127. //interrupt.
unsigned char port1_all1:1; //Port 1 match ALL ONE.
unsigned char port2_all1:1; //Port 2 match ALL ONE.
unsigned char reserved:4; //Reserved Bits.
}PDST;
typedef union
{
unsigned char byte;
PDST bit;
}un_PDST;
//0x03(R)
#define INTR_R_A_TIMER 1
#define INTR_R_B_TIMER 1
#define INTR_R_EXCLK 1
#define INTR_R_P1_CLOCK 1
#define INTR_R_P2_CLOCK 1
typedef struct{ //Interrupt Register.
unsigned char timerA:1; //Timer A interrupt.
unsigned char timerB:1; //Timer B interrupt.
unsigned char ext_clk:1; //External Clock Failure.
unsigned char port1_clk:1; //Data Port l Clock Failure.
unsigned char port2_clk:1; //Data Port 2 Clock Failure.
unsigned char reserved:3; //Reserved Bits.
}INTR;
typedef union
{
unsigned char byte;
INTR bit;
}un_INTR;
// Below define the bit field of write register.
//0x00,0x01(W)
typedef struct{ //General Purpose Output Port
unsigned char cts:1; //CTS
unsigned char dsr:1; //DSR
unsigned char dcd:1; //DCD
unsigned char ri:1; //RI
unsigned char tm:1; //TM
unsigned char protocol:3; //Protocol of Data Port.
}V35_CTL;
typedef union
{
unsigned char byte;
V35_CTL bit;
}un_V35_CTL;
//0x02(W)
#define SELCK_W_SOURCE_E2NREFCK 0
#define SELCK_W_SOURCE_EXTCK 1
#define SELCK_W_SOURCE_NCK1IN 2
#define SELCK_W_SOURCE_NCK2IN 3
#define SELCK_W_SOURCE_INTERNAL 7
typedef struct{ //Reference Clock Source Selector Register.
unsigned char source:3; //Clock Source.
unsigned char reserved:4; //Reserved Bits.
}SELCK;
typedef union
{
unsigned char byte;
SELCK bit;
}un_SELCK;
//0x03(W)
#define RATE_E1 0xff
#define RATE_T1 0xc0
//0x04(W)
#define CTLRATE_W_E1T1_E1 0
#define CTLRATE_W_E1T1_T1 1
#define CTLRATE_W_CLK_FALLING 0
#define CTLRATE_W_CLK_RISING 1
#define CTLRATE_W_NX64_NONFULLRATE 0
#define CTLRATE_W_NX64_FULLRATE 1
#define CTLRATE_W_FRAMEPULSE_EXTERNAL 0
#define CTLRATE_W_FRAMEPULSE_INTERNAL8K 1
#define CTLRATE_W_RESETPD1 1
#define CTLRATE_W_RESETPD2 1
#define CTLRATE_W_INSERTERR_PD1 1
#define CTLRATE_W_INSERTERR_PD2 1
typedef struct{ //
unsigned char e1t1:1; //set_0:1; //Set to 0.
unsigned char clk_rising:1; //Incoming Clock sampling Edge
unsigned char full_rate:1; //Data Port is in Full Rate Application
unsigned char fp_8k:1; //Output 8K Frame Pulse.
unsigned char reset_PD1:1; //Reset Pattern Detector 1.
unsigned char reset_PD2:1; //Reset Pattern Detector 2.
unsigned char insert_err_PG1:1; //Insert one bit error to Test Pattern Generator 1.
unsigned char insert_err_PG2:1; //Insert one bit error to Test Pattern Generator 2.
}CTLRATE;
typedef union
{
unsigned char byte;
CTLRATE bit;
}un_CTLRATE;
//0x05~0x08,0x15~0x18(W)
#define CTLA_W_TIMESLOT_DISABLE 0
#define CTLA_W_TIMESLOT_ENABLE 1
typedef struct{ //Control Register A.
unsigned char ts_0:1; //
unsigned char ts_1:1; //
unsigned char ts_2:1; //
unsigned char ts_3:1; //
unsigned char ts_4:1; //
unsigned char ts_5:1; //
unsigned char ts_6:1; //
unsigned char ts_7:1; //
}CTLA;
typedef union
{
unsigned char byte;
CTLA bit;
}un_CTLA;
//0x09,0x19(W)
#define CTLB_W_OUT_DATA_NORMAL 0
#define CTLB_W_OUT_DATA_INVERSE 1
#define CTLB_W_INPUT_DATA_NORMAL 0
#define CTLB_W_INPUT_DATA_INVERSE 1
#define CTLB_W_RECEIVE_CLOCK_EXTERNAL 0
#define CTLB_W_RECEIVE_CLOCK_INTERNAL 1
#define CTLB_W_RECEIVE_CLOCK_RISING 0
#define CTLB_W_RECEIVE_CLOCK_FALLING 1
#define CTLB_W_WATER_LEVEL_4BYTE 0
#define CTLB_W_WATER_LEVEL_8BYTE 1
#define CTLB_W_WATER_LEVEL_16BYTE 2
#define CTLB_W_WATER_LEVEL_24BYTE 3
#define CTLB_W_WATER_AUTO_RESET 0
#define CTLB_W_RECEIVE_CLOCK_FALLING 1
#define CTLB_W_PORT_DISABLE 0
#define CTLB_W_PORT_ENABLE 1
typedef struct{ //Control Register B.
unsigned char out_data_inv:1; //Inverse Data port Output Data.
unsigned char in_data_inv:1; //Inverse Data port Input Data.
unsigned char sel_clk_int:1; //Use Internal clock as Receive Clock.
unsigned char clk_edge_falling:1; //Use Falling edge of Clock to Sample Receive Data.
unsigned char water_level:2; //Water Level of Internal Buffer.
unsigned char water_reset_auto:1; //Reserved Bit.
unsigned char port_enable:1; //Data Port Enable.
}CTLB;
typedef union
{
unsigned char byte;
CTLB bit;
}un_CTLB;
//0x0a,0x1a(W)
#define CTLC_W_SERVICE_64K 0
#define CTLC_W_SERVICE_56K 1
#define CTLC_W_LOOPBACK_DISABLE 0
#define CTLC_W_LOOPBACK_ENABLE 1
#define CTLC_W_LOOPBACK_DIRECTION_E1T1 0
#define CTLC_W_LOOPBACK_DIRECTION_NX64 1
typedef struct{ //Control Register C.
unsigned char rate:5; //Data Port service Rate.
unsigned char service_56k:1; //Data rate is base on Nx56K.
unsigned char loopback_enable:1; //Loopback Enable.
unsigned char loopback_dir_nx64k:1; //Loopback Direction is on Nx64k direction.
}CTLC;
typedef union
{
unsigned char byte;
CTLC bit;
}un_CTLC;
//0x0b,0x1b(W)
#define CTLD_W_PATTERN_DISABLE 0
#define CTLD_W_PATTERN_GENERATOR 1
#define CTLD_W_PATTERN_RANDOM127 0
#define CTLD_W_PATTERN_ALLONE 1
#define CTLD_W_RANDOM127_INPUT_ZERO 0
#define CTLD_W_RANDOM127_INPUT_ONE 1
#define CTLD_W_PATTERN_INSERT_E1T1 0
#define CTLD_W_PATTERN_INSERT_NX64 1
#define CTLD_W_DETECT_PATTERN_RANDOM127 0
#define CTLD_W_DETECT_PATTERN_ALLONE 1
#define CTLD_W_RANDOM127_OUTPUT_ZERO 0
#define CTLD_W_RANDOM127_OUTPUT_ONE 1
#define CTLD_W_PATTERN_ADAPT_E1T1 0
#define CTLD_W_PATTERN_ADAPT_NX64 1
#define CTLD_W_DETECT_PATTERN_MANU 0
#define CTLD_W_DETECT_PATTERN_AUTO 1
typedef struct{ //Control Register D.
unsigned char PD_enable:1; //Enable Test Pattern Generator.
unsigned char TP_127:1; //Random127 as Test Pattern.
unsigned char TP_127_input_one:1; //Random 127 Test pattern's input data is 1.
unsigned char ins_TP_nx64k:1; //Test Pattern is inserted in Nx64K side.
unsigned char TP_detect_one:1; //Detect Pattern All One.
unsigned char TP_127_output_one:1; //Random 127 Detect pattern's output data is One.
unsigned char TP_adapt_nx64k:1; //Test Pattern is adapt from Nx64K side.
unsigned char TP_auto:1; //Pattern detector from Random 127 to All One in Auto Mode.
}CTLD;
typedef union
{
unsigned char byte;
CTLD bit;
}un_CTLD;
//0x0e,0x1e(W)
#define TCTL_W_TIMER_DISABLE 0
#define TCTL_W_TIMER_ENABLE 1
#define TCTL_W_TIMER_8K_NORMAL 0
#define TCTL_W_TIMER_8K_PREDIVIDE 1
typedef struct{ //Timer Control Register.
unsigned char enable:1; //Enable Timer.
unsigned char pre_div_8k:1; //Pre-devid to 8KHz.
unsigned char reserved:6; //Reserved Bits.
}TCTL;
typedef union
{
unsigned char byte;
TCTL bit;
}un_TCTL;
//0x12(W)
#define INTMK_W_TIMER_INT_DISABLE 0
#define INTMK_W_TIMER_INT_ENABLE 1
#define INTMK_W_EXTCLK_INT_DISABLE 0
#define INTMK_W_EXTCLK_INT_ENABLE 1
#define INTMK_W_DATAP1_CLOCK_FAIL_INT_DISABLE 0
#define INTMK_W_DATAP1_CLOCK_FAIL_INT_ENABLE 1
#define INTMK_W_DATAP2_CLOCK_FAIL_INT_DISABLE 0
#define INTMK_W_DATAP2_CLOCK_FAIL_INT_ENABLE 1
typedef struct{ //Interrupt Mask Register.
unsigned char timerA:1; //Timer A Interrupt Enable.
unsigned char timerB:1; //Timer B Interrupt Enable.
unsigned char ext_clk:1; //External Clock Failure Interrupt Enable.
unsigned char port1_clk:1; //Data Port l Clock Failure Interrupt Enable.
unsigned char port2_clk:1; //Data Port 2 Clock Failure Interrupt Enable.
unsigned char reserved:3; //Reserved Bits.
}INTMK;
typedef union
{
unsigned char byte;
INTMK bit;
}un_INTMK;
//Below define mode pointer of AT9802
typedef struct{
unsigned char byte;
V35_CTL v35_ctl1; //0x00
V35_CTL v35_ctl2; //0x01
SELCK selck; //0x02
//unsigned char rate; //0x03
CTLRATE ctlrate; //0x04
CTLA ctl1a_a; //0x05-0x08
CTLA ctl1a_b; //0x05-0x08
CTLA ctl1a_c; //0x05-0x08
CTLA ctl1a_d; //0x05-0x08
CTLB ctl1b; //0x09
CTLC ctl1c; //0x0a
CTLD ctl1d; //0x0b
//unsigned int timerA; //0x0c-0x0d
TCTL tactl; //0x0e
//unsigned char rstint; //0x0f
//unsigned char reserved10; //0x10
//unsigned char reserved11; //0x11
INTMK intmk; //0x12
//unsigned char reserved13; //0x13
//unsigned char reserved14; //0x14
CTLA ctl2a_a; //0x15-0x18
CTLA ctl2a_b; //0x15-0x18
CTLA ctl2a_c; //0x15-0x18
CTLA ctl2a_d; //0x15-0x18
CTLB ctl2b; //0x19
CTLC ctl2c; //0x1a
CTLD ctl2d; //0x1b
//unsigned int timerB; //0x1c-0x1d
TCTL tbctl; //0x1e
//unsigned char reserved1f; //0x1f
}un_at9802_reg; //AT9802_MODE;
//Below define status pointer of AT9802
typedef struct{
V35_STS v35_sts1; //0x00
V35_STS v35_sts2; //0x01
PDST pdst; //0x02
INTR intr; //0x03
unsigned char ecnta; //0x04
unsigned char ecntb; //0x05
unsigned char reserved[26]; //0x06-0x1f
}AT9802_STATUS;
//Below define write register of AT9802
typedef struct{
unsigned char v35_ctl1; //0x00
unsigned char v35_ctl2; //0x01
unsigned char selck; //0x02
unsigned char rate; //0x03
unsigned char ctlrate; //0x04
unsigned char ctl1a_a; //0x05-0x08
unsigned char ctl1a_b; //0x05-0x08
unsigned char ctl1a_c; //0x05-0x08
unsigned char ctl1a_d; //0x05-0x08
unsigned char ctl1b; //0x09
unsigned char ctl1c; //0x0a
unsigned char ctl1d; //0x0b
unsigned int timerA; //0x0c-0x0d
unsigned char tactl; //0x0e
unsigned char rstint; //0x0f
unsigned char reserved10; //0x10
unsigned char reserved11; //0x11
unsigned char intmk; //0x12
unsigned char reserved13; //0x13
unsigned char reserved14; //0x14
unsigned char ctl2a_a; //0x15-0x18
unsigned char ctl2a_b; //0x15-0x18
unsigned char ctl2a_c; //0x15-0x18
unsigned char ctl2a_d; //0x15-0x18
unsigned char ctl2b; //0x19
unsigned char ctl2c; //0x1a
unsigned char ctl2d; //0x1b
unsigned int timerB; //0x1c-0x1d
unsigned char tbctl; //0x1e
unsigned char reserved1f; //0x1f
}st_at9802;
#define ADDR_AT9802(a) (*(volatile st_at9802 *)a)
#define at9802 ADDR_AT9802(0x4FFFFC00)
#define ABT9802 ADDR_ABYTE(0x4FFFFC00)
#define AGET(x) at.byte = at9802.x
#define ASET(x) at9802.x = at.byte
//Below define read register of AT9802
typedef struct{
unsigned char v35_sts1; //0x00
unsigned char v35_sts2; //0x01
unsigned char pdst; //0x02
unsigned char intr; //0x03
unsigned char ecnta; //0x04
unsigned char ecntb; //0x05
unsigned char reserved[26]; //0x06-0x1f
}AT9802_RDPTR;
/*
typedef union{
AT9802_WRPTR wrptr;
AT9802_RDPTR rdptr;
AT9802_STATUS status;
}AT9802;
typedef union{
AT9802_WRPTR wrptr;
AT9802_MODE mode;
}IMG9802;
*/
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