transcript

SDRAM 控制器

# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/ipcores/sdram_control/sim/sdram_test.mpf" 
# Loading project sdram_test
# Compile of mt48lc2m32b2.v was successful.
# Compile of altera_mf.v was successful.
# Compile of sdr_sdram.v was successful.
# Compile of Command.v was successful.
# Compile of control_interface.v was successful.
# Compile of Params.v was successful.
# Compile of sdr_data_path.v was successful.
# Compile of sdram_test_tb.v was successful.
# 8 compiles, 0 failed with no errors. 
vsim work.sdram_test_tb
# vsim work.sdram_test_tb 
# Loading work.sdram_test_tb
# Loading work.sdr_sdram
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_sdram' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0
# Loading work.control_interface
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_interface' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/control1
# Loading work.command
# ** Warning: (vsim-3009) [TSCALE] - Module 'command' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/command1
# Loading work.sdr_data_path
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_data_path' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/data_path1
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) D:/ipcores/sdram_control/sim/sdram_test_tb.v(351): [PCDPC] - Port size (12 or 12) does not match connection size (11) for port 'SA'.
#         Region: /sdram_test_tb/sdr_sdram0
vsim work.sdram_test_tb
# vsim work.sdram_test_tb 
# Loading work.sdram_test_tb
# Loading work.sdr_sdram
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_sdram' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0
# Loading work.control_interface
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_interface' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/control1
# Loading work.command
# ** Warning: (vsim-3009) [TSCALE] - Module 'command' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/command1
# Loading work.sdr_data_path
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_data_path' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/data_path1
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) D:/ipcores/sdram_control/sim/sdram_test_tb.v(351): [PCDPC] - Port size (12 or 12) does not match connection size (11) for port 'SA'.
#         Region: /sdram_test_tb/sdr_sdram0
view *
# .main_pane.workspace .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.editor .main_pane.activeproc.interior.cs .main_pane.signals.interior.cs .main_pane.signals.interior.cs .main_pane.variables.interior.cs .main_pane.variables.interior.cs .dataflow .list .wave .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page6.cs .main_pane.workspace .main_pane.watch.interior.cs
destroy .list
add wave sim:/sdram_test_tb/*
run
restart
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_sdram' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_interface' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/control1
# ** Warning: (vsim-3009) [TSCALE] - Module 'command' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/command1
# ** Warning: (vsim-3009) [TSCALE] - Module 'sdr_data_path' does not have a `timescale directive in effect, but previous modules do.
#         Region: /sdram_test_tb/sdr_sdram0/data_path1
# ** Warning: (vsim-3015) D:/ipcores/sdram_control/sim/sdram_test_tb.v(351): [PCDPC] - Port size (12 or 12) does not match connection size (11) for port 'SA'.
#         Region: /sdram_test_tb/sdr_sdram0
run