📄 altera_mf.v
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(output_reg == "CLOCK1")? ena1:
(output_reg == "CLOCK2")? ena2:
(output_reg == "CLOCK3")? ena3:1;
assign mult_pipe_wire_en = (multiplier_reg == "UNREGISTERED")? ena0:
multiplier_wire_en;
assign mult_round_wire_en = (mult_round_reg == "UNREGISTERED")? 1:
(mult_round_reg == "CLOCK0")? ena0:
(mult_round_reg == "CLOCK1")? ena1:
(mult_round_reg == "CLOCK2")? ena2:
(mult_round_reg == "CLOCK3")? ena3:1;
assign mult_saturation_wire_en = (mult_saturation_reg == "UNREGISTERED")? 1:
(mult_saturation_reg == "CLOCK0")? ena0:
(mult_saturation_reg == "CLOCK1")? ena1:
(mult_saturation_reg == "CLOCK2")? ena2:
(mult_saturation_reg == "CLOCK3")? ena3:1;
assign accum_round_wire_en = (accum_round_reg == "UNREGISTERED")? 1:
(accum_round_reg == "CLOCK0")? ena0:
(accum_round_reg == "CLOCK1")? ena1:
(accum_round_reg == "CLOCK2")? ena2:
(accum_round_reg == "CLOCK3")? ena3:1;
assign accum_round_pipe_wire_en = (accum_round_pipeline_reg == "UNREGISTERED")? 1:
(accum_round_pipeline_reg == "CLOCK0")? ena0:
(accum_round_pipeline_reg == "CLOCK1")? ena1:
(accum_round_pipeline_reg == "CLOCK2")? ena2:
(accum_round_pipeline_reg == "CLOCK3")? ena3:1;
assign accum_saturation_wire_en = (accum_saturation_reg == "UNREGISTERED")? 1:
(accum_saturation_reg == "CLOCK0")? ena0:
(accum_saturation_reg == "CLOCK1")? ena1:
(accum_saturation_reg == "CLOCK2")? ena2:
(accum_saturation_reg == "CLOCK3")? ena3:1;
assign accum_saturation_pipe_wire_en = (accum_saturation_pipeline_reg == "UNREGISTERED")? 1:
(accum_saturation_pipeline_reg == "CLOCK0")? ena0:
(accum_saturation_pipeline_reg == "CLOCK1")? ena1:
(accum_saturation_pipeline_reg == "CLOCK2")? ena2:
(accum_saturation_pipeline_reg == "CLOCK3")? ena3:1;
// ---------------------------------------------------------
// This block updates the internal clear signals accordingly
// every time the global clear signal changes state
// ---------------------------------------------------------
assign input_a_wire_clr = (input_aclr_a == "UNREGISTERED")? 0:
(input_aclr_a == "ACLR0")? aclr0:
(input_aclr_a == "ACLR1")? aclr1:
(input_aclr_a == "ACLR2")? aclr2:
(input_aclr_a == "ACLR3")? aclr3:0;
assign input_b_wire_clr = (input_aclr_b == "UNREGISTERED")? 0:
(input_aclr_b == "ACLR0")? aclr0:
(input_aclr_b == "ACLR1")? aclr1:
(input_aclr_b == "ACLR2")? aclr2:
(input_aclr_b == "ACLR3")? aclr3:0;
assign addsub_wire_clr = (addnsub_aclr == "UNREGISTERED")? 0:
(addnsub_aclr == "ACLR0")? aclr0:
(addnsub_aclr == "ACLR1")? aclr1:
(addnsub_aclr == "ACLR2")? aclr2:
(addnsub_aclr == "ACLR3")? aclr3:0;
assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "UNREGISTERED")? 0:
(addnsub_pipeline_aclr == "ACLR0")? aclr0:
(addnsub_pipeline_aclr == "ACLR1")? aclr1:
(addnsub_pipeline_aclr == "ACLR2")? aclr2:
(addnsub_pipeline_aclr == "ACLR3")? aclr3:0;
assign zero_wire_clr = (accum_sload_aclr == "UNREGISTERED")? 0:
(accum_sload_aclr == "ACLR0")? aclr0:
(accum_sload_aclr == "ACLR1")? aclr1:
(accum_sload_aclr == "ACLR2")? aclr2:
(accum_sload_aclr == "ACLR3")? aclr3:0;
assign accum_sload_upper_data_wire_clr = (accum_sload_upper_data_aclr == "UNREGISTERED")? 0:
(accum_sload_upper_data_aclr == "ACLR0")? aclr0:
(accum_sload_upper_data_aclr == "ACLR1")? aclr1:
(accum_sload_upper_data_aclr == "ACLR2")? aclr2:
(accum_sload_upper_data_aclr == "ACLR3")? aclr3:0;
assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_pipeline_aclr == "ACLR3")? aclr3:0;
assign accum_sload_upper_data_pipe_wire_clr = (accum_sload_upper_data_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_upper_data_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_upper_data_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_upper_data_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_upper_data_pipeline_aclr == "ACLR3")? aclr3:0;
assign sign_a_wire_clr = (sign_aclr_a == "UNREGISTERED")? 0:
(sign_aclr_a == "ACLR0")? aclr0:
(sign_aclr_a == "ACLR1")? aclr1:
(sign_aclr_a == "ACLR2")? aclr2:
(sign_aclr_a == "ACLR3")? aclr3:0;
assign sign_b_wire_clr = (sign_aclr_b == "UNREGISTERED")? 0:
(sign_aclr_b == "ACLR0")? aclr0:
(sign_aclr_b == "ACLR1")? aclr1:
(sign_aclr_b == "ACLR2")? aclr2:
(sign_aclr_b == "ACLR3")? aclr3:0;
assign input_a_wire_clr = (input_aclr_a == "UNREGISTERED")? 0:
(input_aclr_a == "ACLR0")? aclr0:
(input_aclr_a == "ACLR1")? aclr1:
(input_aclr_a == "ACLR2")? aclr2:
(input_aclr_a == "ACLR3")? aclr3:0;
assign input_b_wire_clr = (input_aclr_b == "UNREGISTERED")? 0:
(input_aclr_b == "ACLR0")? aclr0:
(input_aclr_b == "ACLR1")? aclr1:
(input_aclr_b == "ACLR2")? aclr2:
(input_aclr_b == "ACLR3")? aclr3:0;
assign addsub_wire_clr = (addnsub_aclr == "UNREGISTERED")? 0:
(addnsub_aclr == "ACLR0")? aclr0:
(addnsub_aclr == "ACLR1")? aclr1:
(addnsub_aclr == "ACLR2")? aclr2:
(addnsub_aclr == "ACLR3")? aclr3:0;
assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "UNREGISTERED")? 0:
(addnsub_pipeline_aclr == "ACLR0")? aclr0:
(addnsub_pipeline_aclr == "ACLR1")? aclr1:
(addnsub_pipeline_aclr == "ACLR2")? aclr2:
(addnsub_pipeline_aclr == "ACLR3")? aclr3:0;
assign zero_wire_clr = (accum_sload_aclr == "UNREGISTERED")? 0:
(accum_sload_aclr == "ACLR0")? aclr0:
(accum_sload_aclr == "ACLR1")? aclr1:
(accum_sload_aclr == "ACLR2")? aclr2:
(accum_sload_aclr == "ACLR3")? aclr3:0;
assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "UNREGISTERED")? 0:
(accum_sload_pipeline_aclr == "ACLR0")? aclr0:
(accum_sload_pipeline_aclr == "ACLR1")? aclr1:
(accum_sload_pipeline_aclr == "ACLR2")? aclr2:
(accum_sload_pipeline_aclr == "ACLR3")? aclr3:0;
assign sign_a_wire_clr = (sign_aclr_a == "UNREGISTERED")? 0:
(sign_aclr_a == "ACLR0")? aclr0:
(sign_aclr_a == "ACLR1")? aclr1:
(sign_aclr_a == "ACLR2")? aclr2:
(sign_aclr_a == "ACLR3")? aclr3:0;
assign sign_b_wire_clr = (sign_aclr_b == "UNREGISTERED")? 0:
(sign_aclr_b == "ACLR0")? aclr0:
(sign_aclr_b == "ACLR1")? aclr1:
(sign_aclr_b == "ACLR2")? aclr2:
(sign_aclr_b == "ACLR3")? aclr3:0;
assign sign_pipe_a_wire_clr = (sign_pipeline_aclr_a == "UNREGISTERED")? 0:
(sign_pipeline_aclr_a == "ACLR0")? aclr0:
(sign_pipeline_aclr_a == "ACLR1")? aclr1:
(sign_pipeline_aclr_a == "ACLR2")? aclr2:
(sign_pipeline_aclr_a == "ACLR3")? aclr3:0;
assign sign_pipe_b_wire_clr = (sign_pipeline_aclr_b == "UNREGISTERED")? 0:
(sign_pipeline_aclr_b == "ACLR0")? aclr0:
(sign_pipeline_aclr_b == "ACLR1")? aclr1:
(sign_pipeline_aclr_b == "ACLR2")? aclr2:
(sign_pipeline_aclr_b == "ACLR3")? aclr3:0;
assign multiplier_wire_clr = (multiplier_aclr == "UNREGISTERED")? 0:
(multiplier_aclr == "ACLR0")? aclr0:
(multiplier_aclr == "ACLR1")? aclr1:
(multiplier_aclr == "ACLR2")? aclr2:
(multiplier_aclr == "ACLR3")? aclr3:0;
assign output_wire_clr = (output_aclr == "UNREGISTERED")? 0:
(output_aclr == "ACLR0")? aclr0:
(output_aclr == "ACLR1")? aclr1:
(output_aclr == "ACLR2")? aclr2:
(output_aclr == "ACLR3")? aclr3:0;
assign mult_pipe_wire_clr = (multiplier_reg == "UNREGISTERED")? aclr0:
multiplier_wire_clr;
assign mult_round_wire_clr = (mult_round_aclr == "UNREGISTERED")? 0:
(mult_round_aclr == "ACLR0")? aclr0:
(mult_round_aclr == "ACLR1")? aclr1:
(mult_round_aclr == "ACLR2")? aclr2:
(mult_round_aclr == "ACLR3")? aclr3:0;
assign mult_saturation_wire_clr = (mult_saturation_aclr == "UNREGISTERED")? 0:
(mult_saturation_aclr == "ACLR0")? aclr0:
(mult_saturation_aclr == "ACLR1")? aclr1:
(mult_saturation_aclr == "ACLR2")? aclr2:
(mult_saturation_aclr == "ACLR3")? aclr3:0;
assign accum_round_wire_clr = (accum_round_aclr == "UNREGISTERED")? 0:
(accum_round_aclr == "ACLR0")? aclr0:
(accum_round_aclr == "ACLR1")? aclr1:
(accum_round_aclr == "ACLR2")? aclr2:
(accum_round_aclr == "ACLR3")? aclr3:0;
assign accum_round_pipe_wire_clr = (accum_round_pipeline_aclr == "UNREGISTERED")? 0:
(accum_round_pipeline_aclr == "ACLR0")? aclr0:
(accum_round_pipeline_aclr == "ACLR1")? aclr1:
(accum_round_pipeline_aclr == "ACLR2")? aclr2:
(accum_round_pipeline_aclr == "ACLR3")? aclr3:0;
assign accum_saturation_wire_clr = (accum_saturation_aclr == "UNREGISTERED")? 0:
(accum_saturation_aclr == "ACLR0")? aclr0:
(accum_saturation_aclr == "ACLR1")? aclr1:
(accum_saturation_aclr == "ACLR2")? aclr2:
(accum_saturation_aclr == "ACLR3")? aclr3:0;
assign accum_saturation_pipe_wire_clr = (accum_saturation_pipeline_aclr == "UNREGISTERED")? 0:
(accum_saturation_pipeline_aclr == "ACLR0")? aclr0:
(accum_saturation_pipeline_aclr == "ACLR1")? aclr1:
(accum_saturation_pipeline_aclr == "ACLR2")? aclr2:
(accum_saturation_pipeline_aclr == "ACLR3")? aclr3:0;
// ------------------------------------------------------------------------
// This block contains 1 register and 1 combinatorial block (to set mult_a)
// Signal Registered : dataa
//
// Register is controlled by posedge input_wire_a_clk
// Register has an asynchronous clear signal, input_reg_a_wire_clr
// NOTE : The combinatorial block will be executed if
// input_reg_a is unregistered and dataa changes value
// ------------------------------------------------------------------------
assign mult_a_wire = (input_reg_a == "UNREGISTERED")? mult_a_tmp : mult_a_reg;
assign mult_a_tmp = (input_source_a == "DATAA")? dataa :
(input_source_a == "SCANA")? scanina :
(sourcea == 1)? scanina : dataa;
always @(posedge input_a_wire_clk or posedge input_a_wire_clr)
begin
if (input_a_wire_clr == 1)
mult_a_reg <= 0;
else if ((input_a_wire_clk == 1) && (input_a_wire_en == 1))
begin
if (input_source_a == "DATAA")
mult_a_reg <= dataa;
else if (input_source_a == "SCANA")
mult_a_reg <= scanina;
else if (input_source_a == "VARIABLE")
begin
if (sourcea == 1)
mult_a_reg <= scanina;
else
mult_a_reg <= dataa;
end
end
end
// ------------------------------------------------------------------------
// This block contains 1 register and 1 combinatorial block (to set mult_b)
// Signal Registered : datab
//
// Register is controlled by posedge input_wire_b_clk
// Register has an asynchronous clear signal, input_reg_b_wire_clr
// NOTE : The combinatorial block will be executed if
// input_reg_b is unregistered and datab changes value
// ------------------------------------------------------------------------
assign mult_b_wire = (input_reg_b == "UNREGISTERED")? mult_b_tmp : mult_b_reg;
assign mult_b_tmp = (input_source_b == "DATAB")? datab :
(input_source_b == "SCANB")? scaninb :
(sourceb == 1)? scaninb : datab;
always @(posedge input_b_wire_clk or posedge input_b_wire_clr )
begin
if (input_b_wire_clr == 1)
mult_b_reg <= 0;
else if ((input_b_wire_clk == 1) && (input_b_wire_en == 1))
begin
if (input_source_b == "DATAB")
mult_b_reg <= datab;
else if (input_source_b == "SCANB")
mult_b_reg <= scaninb;
else if (input_source_b == "VARIABLE")
begin
if (sourceb == 1)
mult_b_reg <= scaninb;
else
mult_b_reg <= datab;
end
end
end
// -----------------------------------------------------------------------------
// This block contains 1 register and 1 combinatorial block (to set addnsub_reg)
// Signal Registered : addnsub
//
// Register is controlled by posedge addsub_wire_clk
// Register has an asynchronous clear signal, addsub_wire_clr
// NOTE : The combinatorial block will be executed if
// addnsub_reg is unregistered and addnsub changes value
// -----------------------------------------------------------------------------
assign addsub_wire = ((addnsub_reg == "UNREGISTERED") )? addnsub : addsub_reg;
always @(posedge addsub_wire_clk or posedge addsub_wire_clr)
begin
if (addsub_wire_clr == 1)
addsub_reg <= 0;
else if ((addsub_wire_clk == 1) && (addsub_wire_en == 1))
addsub_reg <= addnsub;
end
// -----------------------------------------------------------------------------
// This block contains 1 register and 1 combinatorial block (to set addsub_pipe)
// Signal Registered : addsub_latent
//
// Register is controlled by posedge addsub_pipe_wire_clk
// Register has an asynchronous clear signal, addsub_pipe_wire_clr
// NOTE : The combinatorial block will be executed if
// addsub_pipeline_reg is unregistered and addsub_latent changes v⌨️ 快捷键说明
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